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data sheet november 2005 fw322 nv129 1394a pci phy/link open host controller interface ? 1 features 129-ball vtfsbga lead-free package. 1394a-2000 ohci link and phy core function in a single device: ? single-chip link and phy enable smaller, sim- pler, more efficient motherboard and add-in card designs. ? compatibility with current microsoft windows ? drivers and common applications. ? interoperability with existing, as well as older, 1394 consumer electronics and peripherals products. ? support low-power system designs (cmos implementation and power management fea- tures). ? lps, lkon, and cna outputs to support legacy power management implementations. ohci: ? complies with the 1394 ohci 1.1 specification . ? ohci 1.0 backwards compatible: configurable via pci bus commands to operate in either ohci 1.0 or ohci 1.1 mode. ? listed on windows hardware compatibility list http://www.microsoft.com/hcl/results.asp. ? compatible with microsoft windows and macos ? operating systems. ? 4 kbyte isochronous transmit fifo. ? 2 kbyte asynchronous transmit fifo. ? 4 kbyte isochronous receive fifo. ? 2 kbyte asynchronous receive fifo. ? dedicated asynchronous and isochronous descriptor-based dma engines. ? eight isochronous transmit/receive contexts. ? prefetches isochronous transmit data. ? supports posted write transactions. ? supports parallel processing of incoming physi- cal read and write requests. ? may be used without an eeprom when the system bios is programmed with the eeprom contents. 1394a-2000 phy core: ? compliant with ieee ? 1394 a-2000, standard for a high performance serial bus . ? provides two fully compliant cable ports, each supporting 400 mbits/s, 200 mbits/s, and 100 mbits/s traffic. ? does not require external filter capacitor for pll. ? supports link-on as a part of the internal phy core-link interface. ? supports arbitrated short bus reset to improve utilization of the bus. ? supports multispeed packet concatenation. ? supports phy pinging and remote phy access packets. ? reports cable power fail interrupt when voltage at cps pin falls below 7.5 v. pci: ? revision 2.2 compliant. ? 33 mhz/32-bit operation. ? programmable burst size thresholds for pci data transfer. ? supports optimized memory read line, memory read multiple, and memory write invalidate burst commands. ? supports pci bus power management interface specification v.1.1. ? supports clkrun# protocol per pci mobile design guide. ? supports mini pci specification v1.0, including mini pci ? power requirements. ? cardbus support per pc card standard release 8.0, including 128 bytes of on-chip tuple memory. 1.1 other features cmos process. 3.3 v operation, 5 v tolerant inputs. i 2 c serial rom interface.
table of contents contents page 2 agere systems inc. data sheet november 2005 pci phy/link open host controller interface fw322 nv129 1394a 1 features ..................................................................................................................... ..................................... 1 1.1 other features ............................................................................................................. .......................... 1 2 fw322 nv129 functional overview .............................................................................................. ................. 7 3 fw322 functional description ................................................................................................. ....................... 7 3.1 pci core ................................................................................................................... .............................. 8 3.2 ohci data transfer ......................................................................................................... ....................... 9 3.3 ohci isochronous data transfer ............................................................................................. .............. 9 3.4 isochronous register access ................................................................................................ ................. 9 3.5 ohci asynchronous data transfer ............................................................................................ .......... 10 3.6 asynchronous register access ............................................................................................... ............. 10 3.7 link core .................................................................................................................. ............................ 12 3.8 phy/link interface ......................................................................................................... ....................... 14 3.9 phy core ................................................................................................................... .......................... 14 4 ball information ............................................................................................................. ................................ 16 5 internal registers ........................................................................................................... ............................... 21 5.1 pci configuration registers ................................................................................................ ................. 21 5.2 vendor id register ......................................................................................................... ...................... 22 5.3 device id register ......................................................................................................... ....................... 22 5.4 pci command register ....................................................................................................... ................. 23 5.5 pci status register ........................................................................................................ ...................... 24 5.6 class code and revision id registers ....................................................................................... ......... 25 5.7 latency timer and cache line size register ................................................................................. ..... 25 5.8 header type and bist register .............................................................................................. ............ 26 5.9 ohci base address register ................................................................................................. .............. 26 5.10 pci subsystem identification register ..................................................................................... ............ 27 5.11 pci power management capabilities pointer register ........................................................................ 27 5.12 interrupt line and pin register ........................................................................................... .................. 27 5.13 min_gnt and max_lat register .............................................................................................. ......... 28 5.14 pci ohci control register ................................................................................................. .................. 28 5.15 capability id and next item pointer register .............................................................................. ......... 29 5.16 power management capabilities register .................................................................................... ....... 30 5.17 power management control and status register .............................................................................. .. 31 5.18 power management csr pci-to-pci bridge support extensions ....................................................... 31 5.19 power management data ..................................................................................................... ................ 32 5.20 ohci registers ............................................................................................................ ........................ 32 5.21 ohci version register ..................................................................................................... .................... 36 5.22 asynchronous transmit retries register .................................................................................... ......... 36 5.23 csr data register ......................................................................................................... ...................... 37 5.24 csr compare register ...................................................................................................... .................. 37 5.25 csr control register ...................................................................................................... ..................... 37 5.26 configuration rom header register ......................................................................................... ........... 38 5.27 bus identification register ............................................................................................... ..................... 38 5.28 bus options register ...................................................................................................... ...................... 39 5.29 guid high register ........................................................................................................ ...................... 39 5.30 guid low register ......................................................................................................... ...................... 40 5.31 configuration rom mapping register ........................................................................................ .......... 40 5.32 posted write address low register ......................................................................................... ............ 40 5.33 posted write address high register ........................................................................................ ............ 41 5.34 vendor id register ........................................................................................................ ....................... 41 5.35 host controller control register .......................................................................................... ................. 42 5.36 selfid buffer pointer register ............................................................................................ .................. 43
data sheet november 2005 table of contents (continued) contents page agere systems inc. 3 pci phy/link open host controller interface fw322 nv129 1394a 5.37 selfid count register ..................................................................................................... ...................... 44 5.38 isochronous receive multiple channel mask high (irmultichanmaskhi) register ............................. 44 5.39 isochronous receive multiple channel mask low (irmultichanmasklo) register ............................. 45 5.40 interrupt event (intevent) register ....................................................................................... ................ 46 5.41 interrupt mask (intmask) register ......................................................................................... ............... 48 5.42 isochronous transmit interrupt event (isoxmitintmask) register ........................................................ 49 5.43 isochronous transmit interrupt mask (isoxmitintmask) register ......................................................... 50 5.44 isochronous receive interrupt event (isorecvintevent) register ........................................................ 51 5.45 isochronous receive interrupt mask (isorecvintmask) register ......................................................... 52 5.46 fairness control register ................................................................................................. .................... 52 5.47 link control register ..................................................................................................... ....................... 53 5.48 node identification register .............................................................................................. .................... 54 5.49 phy core layer control register ........................................................................................... .............. 55 5.50 isochronous cycle timer register .......................................................................................... .............. 55 5.51 asynchronous request filter high register ................................................................................. ........ 56 5.52 asynchronous request filter low register .................................................................................. ........ 56 5.53 physical request filter high register ..................................................................................... ............. 57 5.54 physical request filter low register ...................................................................................... ............. 57 5.55 asynchronous context control register ..................................................................................... .......... 58 5.56 asynchronous context command pointer register ............................................................................. 59 5.57 isochronous transmit context control (it dma contextcontrol) register .......................................... 60 5.58 isochronous transmit context command pointer register ................................................................. 61 5.59 isochronous receive context control (ir dma contextcontrol) register ........................................... 61 5.60 isochronous receive context command pointer register .................................................................. 63 5.61 isochronous receive context match (ir dma contextmatch) register .............................................. 64 5.62 fw322 vendor-specific registers ........................................................................................... ............. 65 5.63 isochronous dma control ................................................................................................... .................. 65 5.64 asynchronous dma control .................................................................................................. ............... 66 5.65 link options .............................................................................................................. ............................ 67 6 internal register configuration .............................................................................................. ....................... 68 6.1 phy core register map ...................................................................................................... ................. 68 6.2 phy core register fields ................................................................................................... .................. 69 7 crystal selection considerations ............................................................................................. ..................... 73 7.1 load capacitance ........................................................................................................... ...................... 73 7.2 adjustment to crystal loading .............................................................................................. ................ 73 7.3 crystal/board layout ....................................................................................................... ..................... 73 8 nand tree testing ............................................................................................................ ........................... 74 9 solder reflow and handling ................................................................................................... ....................... 75 10 absolute maximum voltage/temperature ratings ................................................................................ ........ 75 11 electrical characteristics .................................................................................................. ............................. 76 12 timing characteristics ...................................................................................................... ............................. 78 13 outline diagram ............................................................................................................. ............................... 79 13.1 129-ball vtfsbgac ......................................................................................................... ................... 79 14 ordering information ........................................................................................................ ............................. 80
data sheet november 2005 pci phy/link open host controller interface fw322 nv129 1394a list of figures figure page 4 agere systems inc. figure 1. fw322 nv129 1394a mode block diagram.................................................................................. ........... 7 figure 2. pci core block diagram................................................................................................ ...........................7 figure 3. ohci core block diagram............................................................................................... ......................... 8 figure 4. link core block diagram ............................................................................................... ......................... 11 figure 5. the phy core block diagram ............................................................................................ ....................13 figure 6. ball assignments for the fw322 nv129 .................................................................................. ..............16 figure 7. phy core register map ................................................................................................. ........................68 figure 8. phy core register page 0: port status page............................................................................ ............71 figure 9. phy core register page 1: vendor identification page.................................................................. .......72 figure 10. crystal circuitry .................................................................................................... ..................................73 figure 11. nand tree logic structure ............................................................................................ ........................75
data sheet november 2005 pci phy/link open host controller interface fw322 nv129 1394a list of tables table page agere systems inc. 5 table 1. cable ports ............................................................................................................ .................................. 17 table 2. pci signals ............................................................................................................ .................................. 18 table 3. test, reset, clock, and configuration signals .......................................................................... .............. 19 table 4. power signals.......................................................................................................... ................................ 20 table 5. bit-field access tag description....................................................................................... ...................... 21 table 6. pci configuration register map ......................................................................................... ..................... 21 table 7. pci command register description....................................................................................... ................. 23 table 8. pci status register .................................................................................................... ............................. 24 table 9. class code and revision id register description ........................................................................ .......... 25 table 10. latency timer and class cache line size register description .......................................................... .. 25 table 11. header type and bist register description ............................................................................. ............. 26 table 12. ohci base address register description ................................................................................ .............. 26 table 13. pci subsystem identification register description ..................................................................... ............ 27 table 14. interrupt line and pin register description ........................................................................... ................. 27 table 15. min_gnt and max_lat register description .............................................................................. ........ 28 table 16. pci ohci control register description ................................................................................. ................. 28 table 17. capability id and next item pointer register description.............................................................. ......... 29 table 18. power management capabilities register description .................................................................... ....... 30 table 19. power management control and status register description .............................................................. .. 31 table 20. power management data register description*........................................................................... .......... 32 table 21. ohci register map..................................................................................................... ............................ 33 table 22. ohci version register description..................................................................................... .................... 36 table 23. asynchronous transmit retries register description.................................................................... ......... 36 table 24. csr data register description......................................................................................... ...................... 37 table 25. csr compare register description ...................................................................................... ................. 37 table 26. csr control register description...................................................................................... ..................... 37 table 27. configuration rom header register description ......................................................................... .......... 38 table 28. bus identification register description ............................................................................... .................... 38 table 29. bus options register description ...................................................................................... ..................... 39 table 30. guid high register description ........................................................................................ ..................... 39 table 31. guid low register description ......................................................................................... ..................... 40 table 32. configuration rom mapping register description ........................................................................ ......... 40 table 33. posted write address low register description ......................................................................... ........... 40 table 34. posted write address high register description........................................................................ ............ 41 table 35. vendor id register description........................................................................................ ....................... 41 table 36. host controller control register description .......................................................................... ................ 42 table 37. selfid buffer pointer register description ............................................................................ .................. 43 table 38. selfid count register description ..................................................................................... ..................... 44 table 39. isochronous receive channel mask high register description ............................................................ .44 table 40. isochronous receive channel mask low register description............................................................. .45 table 41. interrupt event register description .................................................................................. ..................... 46 table 42. interrupt mask register description ................................................................................... ..................... 48 table 43. isochronous transmit interrupt event register description............................................................. ....... 49 table 44. isochronous transmit interrupt event description ...................................................................... ............ 50 table 45. isochronous receive interrupt event description ....................................................................... ............ 51 table 46. fairness control register description ................................................................................. ................... 52 table 47. link control register description..................................................................................... ....................... 53 table 48. node identification register description .............................................................................. ................... 54 table 49. phy core layer control register description ........................................................................... ............. 55 table 50. isochronous cycle timer register description .......................................................................... ............. 55 table 51. asynchronous request filter high register description ................................................................. ....... 56
list of tables (continued) table page 6 agere systems inc. data sheet november 2005 pci phy/link open host controller interface fw322 nv129 1394a table 52. asynchronous request filter low register description .................................................................. .......56 table 53. physical request filter high register description ..................................................................... .............57 table 54. physical request filter low register description...................................................................... .............57 table 55. asynchronous context control register description ..................................................................... .........58 table 56. asynchronous context command pointer register description ............................................................. 59 table 57. isochronous transmit context control register description............................................................. ......60 table 58. isochronous transmit context command pointer register description .................................................61 table 59. isochronous receive context control register description.............................................................. ......61 table 60. isochronous receive context command pointer register description ..................................................63 table 61. isochronous receive context match register description ................................................................ .....64 table 62. fw322 vendor-specific registers description ........................................................................... ............65 table 63. isochronous dma control registers description ......................................................................... ...........65 table 64. asynchronous dma control registers description ........................................................................ .........66 table 65. link options register description ..................................................................................... ......................67 table 66. phy core register fields .............................................................................................. .........................69 table 67. phy core register port status page fields ............................................................................. ..............71 table 68. phy core register vendor identification page fields ................................................................... .........72 table 69. nand tree testing ..................................................................................................... ............................74 table 70. absolute maximum ratings.............................................................................................. .......................75 table 71. analog characteristics................................................................................................ .............................76 table 72. driver characteristics ................................................................................................ ..............................77 table 73. device characteristics................................................................................................ .............................77 table 74. switching characteristics ............................................................................................. ...........................78 table 75. clock characteristics................................................................................................. ..............................78
agere systems inc. 7 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 2 fw322 nv129 functional overview agere systems? fw322 nv129 is a high-performance pci bus-based open host controller for implementation of ieee 1394a compliant system or device. figure 1. fw322 nv129 1394a mode block diagram 3 fw322 functional description the fw322 is comprised of four major functional sections (see figure 2): pci core, ohci isochronous and asyn- chronous data transfer, link core, and phy core. the following is a general description of each of the major sec- tions. figure 2. pci core block diagram pci bus pci rom ohci ohci link core data data i/f core cable port 1 cable port 0 transfer transfer asynchronous isochronous core phy slave control master control pci configuration mux address/data pci slave pci master pci bus
8 8 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 3 fw322 functional description (continued) 3.1 pci core the pci core (shown in figure 2) serves as the interface to the pci bus. it contains the state machines that allow the fw322 to respond properly when it is the target of the transaction. also, during 1394 packet transmission or reception, the pci core arbitrates for the pci bus and enables the fw322 to become the bus master for reading the different buffer descriptors and management of the actual data transfers to/from host system memory. the pci core also supports the pci bus power management interface specification v.1.1. included in this support is a standard power management register interface accessible through the pci configuration space. through this register interface, software is able to transition the fw322 into four distinct power states (d0, d1, d2, and d3hot). this permits software to selectively increase/decrease the power consumption of the fw322 for reasons such as periods of system inactivity or power conservation. in addition, the fw322 also includes support for waking up the system through the generation of a power management event (pme). the fw322 supports generation of a power management event (pme) while in the d0, d1, d2, and d3hot power states. figure 3. ohci core block diagram ar fifo at fifo ir fifo it fifo pci slave pci master arbiter ohci interrupt handler pci32 interface asynchronous data transfer isochronous data transfer async register access async rx admin async tx admin selfid dma async_rx dma physical request/ response dma async_tx dma isoch receive dma isoch transmit dma isoch register access register select
agere systems inc. 9 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 3 fw322 functional description (continued) 3.2 ohci data transfer the ohci core consists of the three blocks shown in figure 3: the pci interface (pci32_interface), the isochro- nous data transfer, and the asynchronous data transfer blocks. the pci interface provides an interface between the ohci blocks and the pci core. it contains an arbiter to select the appropriate ohci data engine to gain access to the pci core. in addition, the pci interface includes a register select function to decode slave accesses to the ohci core and select data from appropriate sources. the pci interface also has an ohci interrupt handler to ser- vice ohci generated interrupts, which are ultimately translated into pci interrupts. 3.3 ohci isochronous data transfer the isochronous data transfer logic, which is incorporated into the ohci core, handles the transfer of isochronous data between the link core and the pci interface module. it consists of the isochronous register access module, the isochronous transmit dma module, the isochronous receive dma module, the isochronous transmit (it) fifo, and the isochronous receive (ir) fifo. 3.4 isochronous register access the isochronous register access module services pci slave accesses to ohci registers within the isochronous block. the module also maintains the status of interrupts generated within the isochronous block and sends the isochronous interrupt status to the ohci interrupt handler block. 3.4.1 isochronous transmit dma (itdma) the isochronous transmit dma (itdma) module moves data from host memory to the link core, which will then send the data via the phy core to the 1394 bus. this module consists of eight isochronous transmit contexts, each of which is independently configurable by software, and is capable of sending data on a separate 1394 isochro- nous channel. during each 1394 isochronous cycle, the itdma module will service each of the contexts and attempt to process one 1394 packet for each active context. while processing an active context, itdma will request access to the pci bus. when granted pci access, a descriptor block is fetched from host memory. this data is decoded by itdma to determine how much data is required and where in host memory the data resides. itdma initiates another pci access to fetch this data, which is placed into the isochronous transmit fifo for processing by the link core. if the context is not active, it is skipped by itdma for the current cycle. after processing each context, itdma writes a cycle marker word in the transmit fifo to indicate to the link core that there is no more data for this isochronous cycle. as a summary, the major steps for the fw322 itdma to transmit a packet are the following: 1. fetch a descriptor block from host memory. 2. fetch data specified by the descriptor block from host memory, and place it into the isochronous transmit fifo. 3. data in fifo is read by the link and sent to the phy core device interface. 3.4.2 isochronous receive dma (irdma) the isochronous receive dma (irdma) module moves data from the isochronous receive fifo to host memory. it consists of eight isochronous contexts, each of which is independently controlled by software. normally, each con- text can process data on a single 1394 isochronous channel. however, software can select one context to receive data on multiple channels.
10 10 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 3 fw322 functional description (continued) when irdma detects that the link core has placed data into the receive fifo, it immediately reads out the first word in the fifo, which makes up the header of the isochronous packet. irdma extracts the channel number for the packet and packet filtering controls from the header. this information is compared with the control registers for each context to determine if any context is to process this packet. if a match is found, irdma will request access to the pci bus. when granted pci access, a descriptor block is fetched from host memory. the descriptor provides information about the host memory block allocated for the incoming packet. irdma then reads the packet from the receive fifo and writes the data to host memory via the pci bus. if no match is found, irdma will read the remainder of the packet from the receive fifo, but not process the data in any way. 3.5 ohci asynchronous data transfer the asynchronous data transfer block within the ohci core is functionally partitioned into blocks responsible for processing incoming selfid packet streams, transmitting and receiving asynchronous 1394 packets, processing incoming physical request packets and outgoing physical response packets, and servicing accesses to ohci reg- isters within the respective asynchronous blocks. 3.6 asynchronous register access the asynchronous register access module operates on pci slave accesses to ohci registers within the asynchro- nous block. the module also maintains the status of interrupts generated within the asynchronous block and sends the asynchronous interrupt status to the ohci interrupt handler block. 3.6.1 asynchronous transmit dma (async_tx dma, async_tx_admin) the async_tx dma and async_tx_admin blocks of the fw322 manage the asynchronous transmission of either request or response packets. the mechanism for asynchronous transmission of requests and responses is similar. the only difference is the system memory location of the buffer descriptor list when processing the two con- texts. therefore, the discussion below, which pertains to asynchronous transmit requests, parallels that of asyn- chronous transmit responses. the fw322 asynchronous transmission of packets involves the following steps: 1. fetch complete buffer descriptor block from host memory. 2. get data from system memory and store into asynchronous transmit (at) fifo. 3. request transfer of data from fifo to the link core. 4. handle retries, if any. 5. handle errors in steps 1 to 4. 6. end the transfer if there are no errors. 3.6.2 asynchronous receive dma (async_rx dma, async_rx_admin) the async_rx dma and async_rx_admin blocks of the fw322 manage the processing of received packets. data packets are parsed and stored in a dedicated asynchronous receive (ar) fifo. command descriptors are read through the pci interface to determine the disposition of the data arriving through the 1394 link.
agere systems inc. 11 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 3 fw322 functional description (continued) the header of the received packet is processed to determine, among other things, the following: 1. the type of packet received. 2. the source and destinations. 3. the data and size, if any. 4. any required operation, for example, compare and swap operation. the asynchronous data transfer block also handles dma transfers of selfid packets during the 1394 bus initializa- tion phase and block transactions associated with physical requests. 3.6.3 physical request/response dma the physical dma block within the fw322 is responsible for processing incoming physical requests and outgoing physical responses. when an incoming asynchronous packet is received, the fw322 will process the packet auto- matically without software intervention if the packet meets a set of criteria defined within the ohci specification. when the criteria are met, the asynchronous packet is reclassified as a physical packet. requests that do not meet the criteria remain asynchronous packets and are processed as described above in section 3.6.2. processing packets as physical requests/responses allows the fw322 to either receive or transmit an asynchronous packet without the use of dma descriptors. instead, the fw322 directly writes or reads data to/from memory using the address defined within the packet header. since physical packets can be processed independently of the system?s software and cpu, processing a packet as physical results in a system performance optimization. 3.6.4 selfid dma the selfid dma block within the fw322 is responsible for receiving selfid packets during the bus initialization pro- cess. the received selfid packets are written into a software-defined host memory buffer. figure 4. link core block diagram at fifo isoch control timer tx it fifo crc datamux phy/link interface phydata phyctl phyreq address decoder link control state machine rx interface control ar fifo ir fifo pci slave
12 12 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 3 fw322 functional description (continued) 3.7 link core the link core shown in figure 4 consists of the following blocks: ? link control state machine: main link state machine that controls all other link core modules. ? transmit (tx): reads from the at and it fifos and forms 1394 packets for transmit. ? receive (rx): pipes incoming 1394 packet data to appropriate fifo (if any). ? address decoder: decodes the destination id of an incoming 1394 packet to determine if an acknowledge is needed. ? crc: calculates and checks crc on outgoing and incoming packets. ? isochronous control timer: contains the logic for the 1394 cycle timer. ? datamux: pipes 1394 data to and from various modules. ? interface control: contains interrupt and registers for the link core. interfaces with the slave control block of the pci core. ? phy/link interface: interfaces with the 1394 physical layer. it is the responsibility of the link to ascertain if a received packet is to be forwarded to the ohci for processing. if so, the packet is directed to a proper inbound fifo for either the isochronous block or the asynchronous block to process. the link is also responsible for crc generation on outgoing packets and crc checking on received packets. to become aware of data to be sent outbound on the 1394 bus, the link must monitor the ohci fifos looking for packets in need of transmission. based on data received from the ohci block, the link will form packet headers for the 1394 bus. the link will alert the phy core regarding the availability of the outbound data. it is the link?s function to generate crc for the outbound data. the link also provides phy core register access for the ohci.
agere systems inc. 13 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 3 fw322 functional description (continued) * internal points, inaccessible via external package pins. figure 5. the phy core block diagram link interface i/o received data decoder/ arbitration and control retimer state machine logic bias voltage and current generator cable port 1 oscillator, pll system, and clock generator transmit data encoder cable port 0 tpa0+ tpa0? tpb0+ tpb0? r0 r1 tpbias0 tpbias1 tpa1+ tpa1? tpb1+ tpb1? xi xo lps* sysclk* lreq* ctl0* ctl1* d0* d1* d2* d3* contender* se sm resetn crystal d4* d5* d6* d7* pc0 pc1* pc2* lkon*
14 14 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 3 fw322 functional description (continued) 3.8 phy/link interface the phy/link interface is a direct connection and does not provide isolation. data bits to be transmitted through the cable ports are received from the llc on two, four, or eight data lines (d[0:7]), and are latched internally in the phy in synchronization with the 49.152 mhz system clock. the internal link power status (l:s) signal works with the internal linkon signal to manage the llc power usage of the node. the lps signal indicates that the llc of the node is powered up or down. if lps is inactive for more than 1.2 s and less than 25 s, the internal phy/link interface is reset. if lps is inactive for greater than 25 ms, the phy disables the internal phy/link interface to save power. the fw322 nv129 continues its repeater function. if the phy receives a link-on packet, the internal linkon signal is activated to output a 6.114 mhz signal, which can be used by the llc to power itself up. once the llc is powered up, the internal lps signal communicates this to the phy and the internal phy/link interface is enabled. internal linkon signal is turned off when lctrl bit is set. 3.9 phy core the phy core in figure 5 on the preceding page provides the analog physical layer functions needed to implement a two-port node in a cable-based ieee 1394-1995 and ieee 1394a-2000 network. each cable port incorporates two differential line transceivers. the transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. the phy core interfaces with the link core. the phy core requires either an external 24.576 mhz crystal or crystal oscillator. the internal oscillator drives an internal phase-locked loop (pll) that generates the required 393.216 mhz reference signal. the 393.216 mhz ref- erence signal is internally divided to provide the 49.152 mhz, 98.304 mhz, and 196.608 mhz clock signals that control transmission of the outbound encoded strobe and data information. the 49.152 mhz clock signal is also supplied to the associated link layer controller (llc) for synchronization of the link with the phy core and is used for resynchronization of the received data. the phy/link interface is a direct connection and does not provide isolation. data bits to be transmitted through the cable ports are received from the llc on two, four, or eight data lines (d[0:7]), and are latched internally in the phy in synchronization with the 49.152 mhz system clock. these bits are combined serially, encoded, and transmitted at 98.304 mbits/s, 196.608 mbits/s, or 393.216 mbits/s as the out- bound data-strobe information stream. during transmission, the encoded data information is transmitted differen- tially on the tpa and tpb cable pair(s). during packet reception, the tpa and tpb transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. the encoded data information is received on the tpa and tpb cable pair. the received data strobe information is decoded to recover the receive clock signal and the serial data bits. the serial data bits are split into two (for s100), four (for s200), or eight (for s400) parallel streams, resynchronized to the local system clock, and sent to the associated llc. the received data is also transmitted (repeated) out of the other active (con- nected) cable ports. both the tpa and tpb cable interfaces incorporate differential comparators to monitor the line states during initial- ization and arbitration. the outputs of these comparators are used by the internal logic to determine the arbitration status. the tpa channel monitors the incoming cable common-mode voltage. the value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. in addition, the tpb channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. this monitor is called bias-detect.
agere systems inc. 15 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 3 fw322 functional description (continued) the tpbias circuit monitors the value of incoming tpa pair common-mode voltage when local tpbias is inactive. because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. the monitor is called connect-detect. both the tpb bias-detect monitor and tpbias connect-detect monitor are used in suspend/resume signaling and cable connection detection. the phy core provides a 1.86 v nominal bias voltage for driver load termination. this bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. the value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 v or 3 v nominal supplies. this bias voltage source should be stabilized by using an external filter capacitor of approximately 0.33 f. the port transmitter circuitry and the receiver circuitry are disabled when the port is disabled, suspended, or dis- connected. the line drivers in the phy core operate in a high-impedance current mode and are designed to work with external 112 ? line-termination resistor networks. one network is provided at each end of each twisted-pair cable. each net- work is composed of a pair of series-connected 56 ? resistors. the midpoint of the pair of resistors that is directly connected to the twisted-pair a (tpa) signals is connected to the tpbias voltage signal. the midpoint of the pair of resistors that is directly connected to the twisted-pair b (tpb) signals is coupled to ground through a parallel rc network with recommended resistor and capacitor values of 5 k ? and 220 pf, respectively. the values of the exter- nal resistors are specified to meet the 1394a-2000 specification when connected in parallel with the internal receiver circuits. an external resistor sets the driver output current, along with other internal operating currents. this resistor is con- nected between the r0 and r1 signals and has a value of 2.49 k ? 1%. the c bit (20) in the selfid packet (see section 4.3.4.1 of the ieee 1394a-2000 specification for more details) has a default value of 0, which means this node is not a contender for bus manager. a value of 0 still allows this node to be considered by software for bus manager. the pc0 pin of the device can be tied to v ss to set the power class to 0, or it can be tied to v dd to set the power class to 4. the pc1 and pc2 bits (two least significant bits of the pwr_class field of the selfid packet) are internally tied to 0. when the power supply of the phy core is removed while the twisted-pair cables are connected, the phy core transmitter and receiver circuitry has been designed to present a high impedance to the cable in order to not load the tpbias signal voltage on the other end of the cable. whenever the tpa/tpb signals are wired to a connector, they must be terminated using the normal termination network. this is required for reliable operation. for those applications when one or more of the fw322 ports are not wired to a connector, those unused ports may be left unconnected without normal termination. when a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. the internal link power status (lps) signal works with the internal lkon signal to manage the llc power usage of the node. the lps signal indicates if the llc of the node is powered up or down. if lps is inactive for more than 1.2 s and less than 25 s, the internal phy/link interface is reset. if lps is inactive for greater than 25 s, the phy will disable the internal phy/link interface to save power. the fw322 continues its repeater function even when the phy/link interface is disabled. if the phy then receives a link-on packet, the internal lkon signal is activated to output a 6.114 mhz signal, which can be used by the llc to power itself up. once the llc is powered up, the internal lps signal communicates this to the phy and the inter- nal phy/link interface is enabled. the internal lkon signal is turned off when the lctrl bit is set. five of the fw322 pins are used to set up various test conditions used only during the device manufacturing pro- cess. these pins are se, sm, test0, test1, and test2.
16 16 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 4 ball information note: active-low signals within this document are indicated by an n following the symbol names. figure 6. ball assignments for the fw322 nv129 131211109 8 7654321 v ss a tpb1? tpa1+ tpb0? tpa0+ v dd av dd ar[1] xo sm vaux_ present v dd v ss a nc tpb1+ tpa1? tpb0+ tpa0? tpbias0 r[0] pllv dd xi ptest se v ss card- busn b nc nc nc ? ? ? ? ? ? ? v ss cna nand tree c v dd acps ? nc v ss a tpbias1 v ss apllv ss resetn v ss ? rom_ clk rom_ ad d mpci actn_ 322 lps ? v ss av dd a? ? ? v ss test1 ? test0 pci intan e pc0 pc1 ? lkon ? v ss v ss v ss ? clk runn ? pci gntn pci rstn f pci vios conten der ?pc2? v ss v ss v ss ? pci pmen ?v dd pci reqn g pci ad[1] v dd ? pci ad[0] ?v ss v ss v ss ? pciclk ? pci ad[30] pci ad[31] h pci ad[4] pci ad[3] ? pci ad[2] pci ad[5] ???v ss pci ad[29] ? pci ad[27] pci ad[28] j pci ad[6] pci cben[0] ? pci ad[7] v ss v ss v dd v dd v dd pci ad[25] ? pci ad[24] pci ad[26] k v dd pci ad[8] pci ad[10] ?? ? ???? pci ad[22] pci idsel pci cben[3] l pci ad[9] pci ad[11] pci ad[12] pci ad[14] pci cben[1] pci perrn pci stopn pci irdyn pci cben[2] pci ad[16] pci ad[19] pci ad[20] pci ad[23] m v ss pci ad[13] pci ad[15] pcipar pci serrn pci devseln pci trdyn pci framen pci ad[17] pci ad[18] pci ad[21] v dd v dd n
agere systems inc. 17 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 4 ball information (continued) table 1. cable ports signal listing pin name type name/description a12 tpb1? analog i/o port 1, port cable pair b. tpb1 is the port b connection to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. when the fw322?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal connect-detect circuitry will keep the port in a disconnected state. b12 tpb1+ b11 tpa1? analog i/o port 1, port cable pair a. tpa1 is the port a connection to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. when the fw322?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal connect-detect circuitry will keep the port in a disconnected state. a11 tpa1+ d8 tpbias1 analog i/o port 1, twisted-pair bias. tpbias1 provides the 1.86 v nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. when the fw322?s 1394 port pins are not wired to a connector, the unused port pins may be left uncon- nected. internal connect-detect circuitry will keep the port in a disconnected state. a10 tpb0? analog i/o port 0, port cable pair b. tpb0 is the port b connection to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. when the fw322?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal connect-detect circuitry will keep the port in a disconnected state. b10 tpb0+ b9 tpa0? analog i/o port 0, port cable pair a. tpa0 is the port a connection to the twisted-pair cable. board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. when the fw322?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal connect-detect circuitry will keep the port in a disconnected state. a9 tpa0+ d12 cps i cable power status. cps is normally connected to the cable power through a 400 k ? resistor. this circuit drives an internal comparator that detects the presence of cable power. this information is maintained in one internal register and is avail- able to the llc by way of a register read (see ieee 1394a-2000, standard for a high performance serial bus , sections 4.2.2.7 and 5b.1). note: this pin can be left unconnected for applications that do not use 1394 bus power (vp). when this pin is grounded, the pwr_fail bit in phy register 0101 2 will set. b8 tpbias0 analog i/o port 0, twisted-pair bias. tpbias0 provides the 1.86 v nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. when the fw322?s 1394 port pins are not wired to a connector, the unused port pins may be left uncon- nected. internal connect-detect circuitry will keep the port in a disconnected state.
18 18 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 4 ball information (continued) table 2. pci signals signal listing pin name type name/description h1, h2, h10, h13, j1, j2, j4, j9, j10, j12, j13, l3, l11, l12, k1, k2, k4, k10, k13, m1, m2, m3, m4, m10, m11, m12, m13, n3, n4, n5, n11, n12 pciad[31:0] i/o pci address/data bit. l1, m5, m9, k12 pcicben[3:0] i/o pci command/byte enable signal (active-low). h4 pciclk i pci clock input. 33 mhz. n8 pcidevseln i/o pci device select signal (active-low). n6 pciframen i/o pci frame signal (active-low). f2 pcigntn i pci grant signal (active-low). l2 pciidsel i pci id select. e1 pciintan o pci interrupt (active-low). m6 pciirdyn i/o pci initiator ready signal (active-low). n10 pcipar i/o pci parity signal. m8 pciperrn i/o pci parity error signal (active-low). g4 pcipmen o pci power management event (active-low). a pci power man- agement event will be indicated if this signal is low. g1 pcireqn o pci request signal (active-low). f1 pcirstn i pci reset (active-low). n9 pciserrn i/o pci system error signal (active-low). m7 pcistopn i/o pci stop signal (active-low). n7 pcitrdyn i/o pci target ready signal (active-low). g13 pcivios ? pci signaling indicator. for pci applications that use a universal expansion board (see pci local bus specification , rev. 2.2, sec- tion 4.1.1), connect this pin to the vi/o pin. for other cases, con- nect this pin to 3.3 v for pci buses using 3.3 v signaling or to 5 v for pci buses using 5 v signaling. b1 cardbusn i cardbusn (active-low). selects mode of operation for pci out- put buffers. connect this pin to ground for cardbus operation; con- nect to v dd for pci operation. e13 mpciactn_322 o mini pci function active. output is either asserted or tristated. if output is 0, chip is in a communication state and requires full sys- tem performance. otherwise, the output is tristated (active-low). f4 clkrunn i/o clkrunn (active-low). optional signal for pci mobile comput- ing environment. if not used, clkrunn pin needs to be pulled down to v ss for correct operation.
agere systems inc. 19 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 4 ball information (continued) table 3. test, reset, clock, and configuration signals signal listing pin name type name/description b4 ptest i test. used by agere for device manufacturing testing. tie to v ss for normal operation. d1 rom_ad i/o rom address/data. f10 lkon o link on. signal from the internal phy core to the internal link core. this signal is provided as an output for use in legacy power manage- ment systems. e12 lps o link power status. signal from the internal link core to the internal phy core. lps is provided as an output for use in legacy power management systems. g12 contender i contender. on hardware reset (resetn), this input sets the default value of the contender bit indicated during selfid. this bit can be tied to v dd (high), so it will be considered for bus manager or to ground (low) to not be considered for bus manager. g10 f12 f13 pc2 pc1 pc0 i power-class indicators. on hardware reset (resetn), these inputs set the default value of the power class indicated during selfid. these bits can be tied to v dd (high) or to ground (low) as required for particular power consumption and source characteris- tics. in selfid packet (see section 4.3.4.1 of the 1394a-2000 specifi- cation), pc0, the most significant bit of this 3-bit field, corresponds to bit 21, pc1 corresponds to bit 22, and pc2 corresponds to bit 23. as an example, for a power_class value of 001, pc0 = 0, pc1 = 0, and pc2 = 1. a6 b7 r[1] r[0] i current setting resistor. an internal reference voltage is applied to a resistor connected between r0 and r1 to set the operating current and the cable driver output current. a low temperature-coefficient resistor (tcr) with a value of 2.49 k ? 1% should be used to meet the ieee 1394-1995 standard requirements for output voltage limits. d5 resetn i reset (active-low). when resetn is asserted low (active), a 1394 bus reset condition is set on the active cable ports and the fw322 is reset to the reset start state. to guarantee that the phy will reset, this pin must be held low for at least 2 ms. an internal pull-up resistor, connected to v dd , is provided, so only an external delay capacitor (0.1 f) and resistor (510 k ? ), in parallel, are required to connect this pin to ground. this circuitry will ensure that the capacitor will be discharged when phy power is removed. the input is a standard logic buffer and can also be driven by an open-drain logic output buffer. do not leave this pin unconnected. a4 sm i test mode control. sm is used during agere?s manufacturing test and should be tied to v ss for normal operation. b3 se i test mode control. se is used during agere?s manufacturing test and should be tied to v ss for normal operation. c2 cna o cable not active. cna output is provided for use in legacy power management systems. cna is asserted high when none of the phy ports is receiving an incoming bias voltage. this circuit remains active during the powerdown mode. the cna pin is ttl-compatible. this pin can source and sink up to a 6 ma load. c1 nandtree o nand tree test output. when the chip is placed into the nand tree test mode, the pin is the output of the nand tree logic. this pin is not used during normal operation.
20 20 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 4 ball information (continued) d2 rom_clk i/o rom clock. e2 test0 i test . used by agere for device manufacturing testing. tie to v ss for normal operation. e4 test1 i test . used by agere for device manufacturing testing. tie to v ss for normal operation. b5 xi analog i/o crystal oscillator. xi and xo connect to a 24.576 mhz parallel res- onant fundamental mode crystal. although when a 24.576 mhz clock source is used, it can be connected to xi with xo left unconnected. the optimum values for the external shunt capacitors are dependent on the specifications of the crystal used. it is necessary to add an external series resistor to the xo pin. the value of the resistor is nominally 400 ? . note that it is very important to place the crystal as close as possible to the xo and xi pins (i.e., within 0.5 in./1.27 cm). for more important details regarding the crystal, refer to the fw323/ fw322 hardware implementation design guideline application note . a5 xo table 4. power signals signal listing pin name type name/description a1, b2, c3, d4, e5, f6, f7, f8, g6, g7, g8, h6, h7, h8, j5, k8, k9, n13 v ss ? digital ground. a2, g2, h12, k5, k6, k7, l13, n1, n2 v dd ? digital power. a7, a8, d13, e9 v dd a ? analog circuit power. v dd a supplies power to the analog portion of the device. a13, d9, d7, e10 v ss a ? analog circuit ground. all v ss a signals should be tied together to a low-impedance ground plane. b6 pllv dd ? power for pll circuit. pllvdd supplies power to the pll circuitry portion of the device. d6 pllv ss ? ground for pll circuit. pllvss is tied to a low-impedance ground plane. a3 vaux_present i 3.3 v aux present. an active-high input indicating whether the fw322 is powered via an auxiliary power supply (e.g., pci 3.3 v aux ). an internal pull-down resistor connected to v ss is provided, so an external pull-up is only required when the device is being powered by an auxiliary power supply. note that vaux_present is not an actual power supply pin to the device. rather, this pin is an indicator of whether the fw322 is powered via an auxiliary power supply (vaux_present = 1) or the regular pci power supply (vaux_present = 0). this input is used by the fw322 to properly support the d3cold power management functionality. b13, c11, c12, c13, d10 nc ? no connect. table 3. test, reset, clock, and configuration signals (continued) signal listing pin name type name/description
agere systems inc. 21 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers this section provides a summary of the internal registers within the fw322, including both pci configuration regis- ters and ohci registers. register default values, registers, and bits that have not been implemented in the fw322, and other information specific to the fw322 will be noted. please refer to the pci local bus specification v.2.2, pci bus power management interface specification , v.1.1, 1394 ohci specification v.1.1, and the ieee standard 1394a-2000 specification for further details concerning these registers. table 5 describes the field access tags that are designated in the type column of the register tables in this docu- ment. 5.1 pci configuration registers table 6 illustrates the pci configuration header that includes both the predefined portion of the configuration space and the user-definable registers. table 5. bit-field access tag description access tag name description r read field may be read by software. w write field may be written by software to any value. s set field may be set by a write of 1. writes of 0 have no effect. c clear field may be cleared by a write of 1. writes of 0 have no effect. u update field may be autonomously updated by the fw322 . table 6. pci configuration register map register name (default) offset device id [5811h] vendor id [11c1h] 00h status [02901h] command [0000h] 04h class code [0c0010h] revision id [6xh] * 08h bist [00h] header type [00h] latency timer ? [00h] cache line size ? [00h] 0ch ohci base address register [0000 0000h] 10h reserved 14h reserved 18h reserved 1ch reserved 20h reserved 24h cardbus cis pointer [0000 0000h] 28h subsystem id ? [0000h] subsystem vendor id ? [0000h] 2ch reserved 30h reserved pci power manage- ment capabilities pointer [44h] 34h reserved 38h maximum latency ? [18h] minimum grant ? [0ch] interrupt pin [01h] interrupt line [00h] 3ch * x is a minor revision number of the fw322 t100 and may be any value from 0 hex to f hex. ? the hardware default value for this regi ster can be altered with a pci bus command.
22 22 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.2 vendor id register the vendor id register contains a value allocated by the pci sig and identifies the manufacturer of the device. the vendor id assigned to agere is 11c1h. offset: 00h default: 11c1h type: read only reference: pci local bus specification , rev. 2.2, section 6.2.1 5.3 device id register the device id register contains a value assigned to the fw322 by agere. the device identification for the fw322 is 5811h. offset: 02h default: 5811h type: read only reference: pci local bus specification , rev. 2.2, section 6.2.1 table 6. pci configuration register map (continued) register name (default) offset pci ohci control register ? [0000 0000h] 40h power management capabilities ? [7e02h] next item pointer [00h] capability id [01h] 44h pm data ? [00h] pmcsr_bse [00h] power management csr ? [0000h] 48h reserved 4c?fch * x is a minor revision number of the fw322 t100 and may be any value from 0 hex to f hex. ? the hardware default value for this regi ster can be altered with a pci bus command.
agere systems inc. 23 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.4 pci command register the command register provides control over the fw322 interface to the pci bus. all bit functions adhere to the def- initions in the pci local bus specification , as in the following bit descriptions. offset: 04h default: 0000h type: read/write reference: pci local bus specification , rev. 2.2, section 6.2.2 and 1394 open host controller interface specification , rev. 1.1, section a.3.1 table 7. pci command register description bit field name type description 15:10 reserved r reserved. bits 15:10 return 0s when read. 9fbb_enbr fast back-to-back enable. the fw322 does not generate fast back-to- back transactions; thus, this bit returns 0 when read. 8 serr_enb rw serr enable. when this bit is set, the fw322 serr driver is enabled. pci_serrn can be asserted after detecting an address parity error on the pci bus. 7 step_enb r address/data stepping control. the fw322 does not support address/data stepping; thus, this bit is hardwired to 0. 6 perr_enb rw parity error enable. when this bit is set, the fw322 is enabled to drive perr response to parity errors through the pci_perrn signal. 5vga_enbr vga palette snoop enable. the fw322 does not feature vga palette snooping. this bit returns 0 when read. 4mwi_enbrw memory write and invalidate enable. when this bit is set, the fw322 is enabled to generate mwi pci bus commands. if this bit is reset, then the fw322 generates memory write commands instead. 3specialr special cycle enable. the fw322 function does not respond to special cycle transactions. this bit returns 0 when read. 2 master_enb rw bus master enable. when this bit is set, the fw322 is enabled to initiate cycles on the pci bus. 1 memory_enb rw memory response enable. setting this bit enables the fw322 to respond to memory cycles on the pci bus. this bit must be set to access ohci registers. 0io_enbr i/o space enable . the fw322 does not implement any i/o mapped functionality; thus, this bit returns 0 when read.
24 24 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.5 pci status register the status register provides status information for pci bus related events. all bit functions adhere to the definitions in the pci local bus specification , v.2.2, table 6.2. offset: 06h default: 0290h type: read/write reference: pci local bus specification , rev. 2.2, section 6.2.3 and 1394 open host controller interface specification , rev. 1.1, section a.3.2 table 8. pci status register bit field name type description 15 par_err rcu detected parity error. this bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled. 14 sys_err rcu signaled system error. this bit must be set whenever the device asserts serr#. 13 mabort rcu received master abort. this bit must be set by a master device when- ever its transaction (except for special cycle) is terminated with master- abort. 12 tabort_rec rcu received target abort. this bit must be set by a master device when- ever its transaction is terminated with target-abort. 11 tabort_sig rcu signaled target abort. this bit must be set by a target device when- ever it terminates a transaction with target-abort. 10:9 pci_speed r devsel timing. bits 9 and 10 encode the timing of delsel# (see section 3.6.1 of the pci specification). these bits must indicate the slow- est time that a device asserts devsel# for any bus command except configuration read and configuration write. the default timing is 01 (medium). 8 datapar rcu master data parity error. see table 6-2 of the pci specification for more information. 7fbb_cap r fast back-to-back capable. this bit indicates whether or not the target is capable of accepting fast back-to-back transactions when the transac- tions are not to the same agent. the fw322 does not support back-to- back transactions. 6 reserved r reserved . 5 66mhz r 66 mhz capable. this bit indicates whether or not this device is capable of running at 66 mhz as defined in chapter 7 of the pci specification. the fw322 reports a value of zero in this field indicating that 66 mhz functionality is not supported. 4caplist r capabilities list. this bit indicates whether or not this device imple- ments the pointer for a new capabilities linked list at offset 34h. a value of zero indicates that no new capabilities linked list is available. a value of one indicates that the value read at offset 34h is a point in configura- tion space to a linked list of new capabilities. (see section 6.7 of the pci specification for more details.) 3:0 reserved r reserved .
agere systems inc. 25 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.6 class code and revision id registers the class code register and revision id register categorize the fw322 as a serial bus controller (0ch), controlling an ieee 1394 bus (00h), with an ohci programming model (10h). furthermore, the chip revision is indicated in the lower byte. offset: 08h default: 0c00 106xh type: read only reference: pci local bus specification , rev. 2.2, section 6.2.1 and 1394 open host controller interface specification , rev. 1.1, section a.3.3 and a.3.4 5.7 latency timer and cache line size register the latency timer and class cache line size register is programmed by host bios to indicate system cache line size and the latency timer associated with the fw322. on powerup, the hardware default value will be loaded, but an alternative value may be loaded using a pci bus command. offset: 0ch default: 0000h type: read/write reference: pci local bus specification , rev. 2.2, section 6.2.4 table 9. class code and revision id register description bit field name type description 31:24 baseclass r base class. this field returns 0ch when read, which classifies the func- tion as a serial bus controller. 23:16 subclass r subclass. this field returns 00h when read, which specifically classifies the function as an ieee 1394 serial bus controller. 15:8 pgmif r programming interface. this field returns 10h when read, indicating that the programming model is compliant with the 1394 open host con- troller interface specification . 7:0 chiprev r silicon revision. this field returns 6xh* when read, indicating the sili- con revision of the fw322. * x is a minor revision number of the fw322 t100 and may be any value from 0 hex to f hex. table 10. latency timer and class cache line size register description bit field name type description 15:8 latency_timer rw pci latency timer. the value in this register specifies the latency timer, in units of pci clock cycles, for the fw322. when the fw322 is a pci bus initiator and asserts frame, the latency timer begins count- ing from zero. if the latency timer expires before the fw322 transac- tion has terminated, then the fw322 terminates the transaction when its pci_gntn is deasserted. 7:0 cacheline_sz rw cache line size. this value is used by the fw322 during memory write and invalidate, memory read line, and memory read multiple transactions.
26 26 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.8 header type and bist register the header type and bist register indicates the fw322 pci header type. offset: 0eh default: 0000h type: read only reference: pci local bus specification , rev. 2.2, sections 6.2.1 and 6.2.4 5.9 ohci base address register the ohci base address register is programmed with a base address referencing the memory-mapped ohci con- trol. when bios writes all 1s to this register, the value read back is ffff f000h, indicating that 4 kbytes of mem- ory address space are required for the ohci registers. offset: 10h default: 0000 0000h type: read/write reference: pci local bus specification , rev. 2.2, sections 6.2.5 and 1394 open host controller interface specification , rev. 1.1, section a.3.5 table 11. header type and bist register description bit field name type description 15:8 bist r built-in self-test. the fw322 does not include a built-in self-test; thus, this field returns 00h when read. 7:0 header_type r pci header type. the fw322 includes the standard pci header, and this is communicated by returning 00h when this field is read. table 12. ohci base address register description bit field name type description 31:12 ohcireg_ptr rw ohci register pointer. this field specifies the upper 20 bits of the 32-bit ohci base address. 11:4 ohci_sz r ohci register size. this field returns 0s when read, indicating that the ohci registers require a 4 kbyte region of memory. 3 ohci_pf r ohci register prefetch. this bit returns 0 when read, indicating that the ohci registers are not prefetchable. 2:1 ohci_memtype r ohci memory type. this field returns 0s when read, indicating that the ohci base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 ohci_mem r ohci memory indicator. this bit returns 0 when read, indicating that the ohci registers are mapped into system memory space.
agere systems inc. 27 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.10 pci subsystem identification register the pci subsystem identification register is used to uniquely identify the card or system in which the fw322 resides. subsystem vendor ids can be obtained from the pci sig. values for the subsystem id are vendor spe- cific. on powerup, the hardware default value will be loaded. however, a nonzero value should be loaded into this regis- ter by the bios, operating system, etc., using a pci bus command. by default, the pci subsystem id and pci sub- system vendor id registers are read-only. in order to load this register, first set the subsystemwriteen bit, bit 0 of the pci configuration register offset 4ch, which will enable writes to the pci subsystem id and pci subsystem vendor id registers. after the ids have been written, the subsystemwriteen bit should be reset to protect the data from being overwritten. offset: 2ch default: 0000 0000h type: read/write reference: pci local bus specification , rev. 2.2, section 6.2.4 5.11 pci power management capabilities pointer register the pci power management capabilities pointer register provides a pointer into the pci configuration header where the pci power management register block resides. the fw322 configuration words at offsets 44h and 48h provide the power management registers. this register is read-only and returns 44h when read. offset: 34h default: 44h type: read only reference: pci local bus specification , rev. 2.2, section 6.2.4 and 6.7 and 1394 open host controller inter- face specification , rev. 1.1, section a.3.6 5.12 interrupt line and pin register the interrupt line and pin register is used to communicate interrupt line routing information. offset: 3ch default: 0100h type: read only reference: pci local bus specification , rev. 2.2, section 6.2.4 and 6.7 table 13. pci subsystem identification register description bit field name type description 31:16 ssid ru subsystem id. this field indicates the subsystem id. 15:0 ssvid ru subsystem vendor id. this field indicates the subsystem vendor id. table 14. interrupt line and pin register description bit field name type description 15:8 intr_pin r interrupt pin register. this register returns 01h when read, indicating that the fw322 pci function signals interrupts on the inta pin. 7:0 intr_line rw interrupt line register. this register is programmed by the system and indicates to software to which interrupt line the fw322 inta is connected.
28 28 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.13 min_gnt and max_lat register the min_gnt and max_lat register is used to communicate to the system the desired setting of the latency timer register. on powerup, the hardware default value will be loaded, but an alternative value may be loaded using a pci bus command. offset: 3eh default: 180ch type: read only reference: pci local bus specification , rev. 2.2, section 6.2.4 5.14 pci ohci control register the pci ohci control register is defined in section a.3.7 of the 1394 open host controller interface specification and provides a bit for big-endian pci support. on powerup, the hardware default value will be loaded, but an alter- native value may be loaded using a pci bus command. offset: 40h default: 0000 0000h type: read/write reference: 1394 open host controller interface specification , rev. 1.1, section a.3.7 table 15. min_gnt and max_lat register description bit field name type description 15:8 max_lat ru maximum latency. the contents of this register may be used by host bios to assign an arbitration priority level to the fw322. the default for this register (18h) indicates that the fw322 may need to access the pci bus as often as every 0.25 s; thus, an extremely high-priority level is requested. the contents of this field may also be loaded using a pci bus command. 7:0 min_gnt ru minimum grant. the contents of this register may be used by host bios to assign a latency timer register value to the fw322. the default (0ch) for this register indicates that the fw322 may need to sustain burst transfers for nearly 64 s, thus requesting a large value be programmed in the fw322 latency timer register. the contents of this field may also be loaded using a pci bus command. table 16. pci ohci control register description bit field name type description 31:1 reserved r reserved. bits 31:1 return 0s when read. 0 global_swap rw when this bit is set, all quadlets read from the fw322 as well as any data written to the pci bus by the fw322 is byte swapped. this excludes pci configuration registers (they are not swapped under any circumstances). however, ohci registers are byte-swapped when this bit is set.
agere systems inc. 29 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.15 capability id and next item pointer register the capability id and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item. offset: 44h default: 0001h type: read only reference: pci local bus specification , rev. 2.2, sections 6.8.1.1, 6.8.1.2 and 1394 open host controller interface specification , rev. 1.1, sections a.3.8.1 and a.3.8.2 table 17. capability id and next item pointer register description bit field name type description 15:8 next_item r next item pointer. the fw322 supports only one additional capability that is communicated to the system through the extended capabilities list; thus, this field returns 00h when read. 7:0 capability_id r capability identification. this field returns 01h when read, which is the unique id assigned by the pci sig for pci power management capability.
30 30 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.16 power management capabilities register the power management capabilities register indicates the capabilities of the fw322 related to pci power manage- ment. on powerup, the default value will be loaded. offset: 46h default: 7e02h type: read only reference: pci bus power management interface specification , rev. 1.1, section 3.2.3 and 1394 open host controller interface specification , rev. 1.1, section a.3.8.3 table 18. power management capabilities register description bit field name type description 15 pme_d3cold r pme support from d3cold. this bit is set to 0, indicating that the fw322 cannot generate a pme event in d3cold. 14 pme_d3hot r pme support from d3hot. this bit is set to 1, indicating that the fw322 can generate a pme event in the d3hot state. 13 pme_d2 r pme support from d2. this bit is set to 1, indicating that the fw322 can generate a pme in d2. 12 pme_d1 r pme support from d1. this bit is set to 1, indicating that the fw322 can generate a pme in d1. 11 pme_d0 r pme support from d0. this bit is set to 1, indicating that the fw322 can generate a pme in d0. 10 d2_support r d2 support. this bit returns a 1 when read, indicating that the fw322 supports the d2 power state. 9 d1_support r d1 support. this bit returns a 1 when read, indicating that the fw322 supports the d1 power state. 8:6 aux_pwr r auxiliary power source . this field reports the v aux power require- ments for the open hci function. this field is always 0. 5dsir device-specific initialization. this bit returns 0 when read, indicating that the fw322 does not require special initialization beyond the stan- dard pci configuration header before a generic class driver is able to use it. 4 reserved r reserved . bit returns 0 when read. 3 pme_clk r pme clock. this bit returns 0 when read, indicating that no host bus clock is required for the fw322 to generate pme. 2:0 pm_version r power management version. this field returns 010b when read, indi- cating that the fw322 is compatible with the registers described in the pci power management interface specification , rev.1.1.
agere systems inc. 31 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.17 power management control and status register the power management control and status register implements the control and status of the pci power manage- ment function. this register is not affected by the internally generated reset caused by the transition from the d3hot to d0 state. all bits within this register will be reset by a pci reset. offset: 48h default: xx00h type: read/write reference: pci bus power management interface specification , rev. 1.1, section 3.2.4 and 1394 open host controller interface specification , rev. 1.1, section a.3.8.4 5.18 power management csr pci-to-pci bridge support extensions this register returns 00h when read since the fw322 does not provide pci-to-pci bridging. offset: 4ah default: 00h type: read only reference: pci bus power management interface specification , rev. 1.1, section 3.2.5 and 1394 open host controller interface specification , rev. 1.1, section a.3.8.5 and a.3.8.6 table 19. power management control and status register description bit field name type description 15 pme_sts rc this bit is set when the fw322 would normally be asserting the pme signal, independent of the state of the pme_enb bit. this bit is cleared by a writeback of 1, and this also clears the pme signal driven by the fw322. writing a 0 to this bit has no effect. 14:13 data_scale r this 2-bit field indicates a scaling factor that is to be used when inter- preting the value of the pm_data register within the power manage- ment extension register. the value and meaning of this field will vary depending on the value that has been selected by the data_select field. 12:9 data_select r this 4-bit field is used to select which data values are to be reported through the pm_data field in the power management extension regis- ter and the data_scale fields. valid values are 0?7, which map to power consumption/dissipation ratings for the fw322 within the pm_data/data_scale fields. 8pme_enbrw pme enable. this bit enables the function to assert pme. if this bit is cleared, then assertion of pme is disabled. 7:5 reserved r reserved. bits 7:5 return 0s when read. 4dyn_datar dynamic data . this bit returns 0 when read, since the fw322 does not report dynamic data. 3:2 reserved r reserved. bits 3:2 return 0s when read. 1:0 pwr_state rw power state . this 2-bit field is used to set the fw322 device power state and is encoded as follows: 00 = current power state is d0. 01 = current power state is d1. 10 = current power state is d2. 11 = current power state is d3.
32 32 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.19 power management data the power management (pm) data register set is comprised of 16 eight-bit registers, providing more detailed power management information about the device. all 16 registers will return 00h by default. the first eight registers are assigned to single function devices, and the second eight are reserved for use by multifunction devices (see table 20). the fw322 supports programmability, via pci bus commands, of the first eight registers in the pm data complex. software uses the data_select and data_scale fields within the power management control and status register to select and scale the desired pm data entry. offset: 4bh default: 00h type: read only reference: pci bus power management interface specification , rev. 1.1, section 3.2.6 and 1394 open host controller interface specification , rev. 1.1, section a.3.8.5 and a.3.8.6 * derived from table 10 of the pci power management interface specification, revision 1.1. 5.20 ohci registers the ohci registers defined by the 1394 open host controller interface specification are memory-mapped into a 2 kbyte region of memory pointed to by the ohci base address register located at offset 10h in pci configuration space. these registers are the primary interface for controlling the fw322 ieee 1394 ohci function. this section provides a summary of the registers within this interface and a description of the individual bit fields within each register. for more details regarding these registers and bits, please refer to the 1394 open host controller inter- face specification , rev. 1.1. in addition to regular read/write registers, there are several pairs of set and clear registers implemented within the ohci register interface. for each pair of set and clear registers, there are two addresses that correspond to indi- vidual set/clear registers: registerset and registerclear. a 1 bit written to registerset causes the corresponding bit in the register to be set, while a 0 bit leaves the corresponding bit unaffected. a 1 bit written to registerclear causes the corresponding bit in the register to be reset, while a 0 bit leaves the corresponding bit unaffected. typi- cally, a read from either registerset or registerclear returns the contents of the set or clear register. however, in some instances, reading the registerclear provides a masked version of the set or clear register. the interrupt event register is an example of this behavior. the following fw322 ohci register definitions are based on version 1.1 of the 1394 open host controller specifi- cation . table 20. power management data register description* value in data_select data reported data_scale interpretation unit/accuracy 0 d0 power consumed 0 = unknown 1 = 0.1x 2 = 0.01x 3 = 0.001x w 1 d1 power consumed 2 d2 power consumed 3 d3 power consumed 4 d0 power dissipated 5 d1 power dissipated 6 d2 power dissipated 7 d3 power dissipated 8?15 reserved (unused by fw322 and will return 00h when read) reserved tbd
agere systems inc. 33 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) table 21. ohci register map dma context register name abbreviation offset ohci specification reference ? ohci version version 00h 5.2 global unique id rom* guid_rom 04h 5.3 asynchronous transmit retries atretries 08h 5.4 csr data csrdata 0ch 5.5.1 csr compare data csrcomparedata 10h csr control csrcontrol 14h configuration rom header configromhdr 18h 5.5.2 bus identification busid 1ch 5.5.3 bus options busoptions 20h 5.5.4 global unique id high guidhi 24h 5.5.5 global unique id low guidlo 28h reserved ? 2ch ? reserved ? 30h ? configuration rom map configrommap 34h 5.5.6 posted write address low postedwriteaddresslo 38h 13.2.8.1 posted write address high postedwriteaddresshi 3ch vendor identification vendorid 40h 5.6 reserved ? reserved ? host controller control hccontrolset 50h 5.7 hccontrolclear 54h reserved ? 58h ? reserved ? 5ch ? reserved ? 60h ? selfid selfid buffer selfidbuffer 64h 11.1 selfid count selfidcount 68h 11.2 reserved ? 6ch ? ? isochronous receive channel mask high irchannelmaskhiset 70h 10.4.1.1 irchannelmaskhiclear 74h isochronous receive channel mask low irchannelmaskloset 78h irchannelmaskloclear 7ch interrupt event inteventset 80h 6.1 inteventclear 84h interrupt mask intmaskset 88h 6.2 intmaskclear 8ch isochronous transmit interrupt event isoxmitinteventset 90h 6.3.1 isoxmitinteventclear 94h isochronous transmit interrupt mask isoxmitintmaskset 98h 6.3.2 isoxmitintmaskclear 9ch * since the fw322 v129 does not support an eeprom, this register is not used.
34 34 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) table 21. ohci register map (continued) dma context register name abbreviation offset ohci specification reference ? isochronous receive interrupt event isorecvinteventset a0h 6.4.1 isorecvinteventclear a4h isochronous receive interrupt mask isorecvintmaskset a8h 6.4.2 isorecvintmaskclear ach bus management csr initialization initialbandwidthavailable b0h 5.8 initialchannelsavailablehi b4h initialchannelsavailablelo b8h reserved ? bch:d8h ? fairness control fairnesscontrol dch 5.9 link control linkcontrolset e0h 5.10 linkcontrolclear e4h node identification nodeid e8h 5.11 phy core layer control phycontrol ech 5.12 isochronous cycle timer isocyctimer f0h 5.13 reserved ? f4h:fch ? asynchronous request filter high asyncrequestfilterhiset 100h 5.14.1 asyncrequestfilterhiclear 104h asynchronous request filter low asyncrequestfilterloset 108h asyncrequestfilterloclear 10ch physical request filter high physicalrequestfilterhiset 110h 5.4.2 physicalrequestfilterhiclear 114h physical request filter low physicalrequestfilterloset 118h physicalrequestfilterloclear 11ch physical upper bound physicalupperbound 120h 5.15 reserved ? 124h:17ch ? asynchronous request transmit [atrq] context control contextcontrolset 180h 3.1, 7.2.2 contextcontrolclear 184h reserved ? 188h ? command pointer commandptr 18ch 3.1.2, 7.2.1 asynchronous response transmit [atrs] reserved ? 190h:19ch ? context control contextcontrolset 1a0h 3.1, 7.2.2 contextcontrolclear 1a4h reserved ? 1a8h ? command pointer commandptr 1ach 3.1.2, 7.2.1 asynchronous request receive [arrq] reserved ? 1b0h:1bch ? context control contextcontrolset 1c0h 3.1, 8.3.2 contextcontrolclear 1c4h reserved ? 1c8h ? command pointer commandptr 1cch 3.1.2, 8.3.1 * since the fw322 v129 does not support an eeprom, this register is not used.
agere systems inc. 35 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) table 21. ohci register map (continued) dma context register name abbreviation offset ohci specification reference asynchronous response receive [arrs] reserved ? 1d0h:1dfh ? context control contextcontrolset 1e0h 3.1, 8.3.2 contextcontrolclear 1e4h reserved ? 1e8h ? command pointer commandptr 1ech 3.1.2, 8.3.1 isochronous transmit context n n = 0:7 reserved ? 1f0h:1ffh ? context control contextcontrolset 200h + 16 * n 3.1, 9.2.2 contextcontrolclear 204h + 16 * n reserved ? 208h + 16 * n ? command pointer commandptr 20ch + 16 * n 3.1.2, 9.2.1 isochronous receive context n n = 0:7 context control contextcontrolset 400h + 32 * n 3.1, 10.3.2 contextcontrolclear 404h + 32 * n reserved ? 408h + 32 * n ? command pointer commandptr 40ch + 32 * n 3.1.2, 10.3.1 context match contextmatch 410h + 32 * n 10.3.3 reserved ? 414h + 32 * n ? 41ch + 32 * n ? * since the fw322 v129 does not support an eeprom, this register is not used.
36 36 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.21 ohci version register this register indicates the ohci version supported. to support backwards compatibility with existing hardware and software, the version and revision fields default to 8?h01 and 8?h00 respectively. these values denote compatibility with version 1.0 of the ohci specification. however, both the version and revision fields are programmable via pci bus commands. this functionality allows these fields to be optionally updated to 8?h01 and 8?h10 respectively to indicate compatibility with version 1.1 of the ohci specification. note that if the version and revision fields are pro- grammed with ohci 1.1 values, then the linkoptions register (see section 5.62) should also be programmed to properly enable ohci 1.1 features within the fw322. offset: 00h default: 0x01 0000h type: read/write reference: 1394 open host controller interface specification , rev. 1.1, section 5.2 5.22 asynchronous transmit retries register the asynchronous transmit retries register indicates the number of times the fw322 attempts a retry for asynchro- nous dma request transmit and for asynchronous physical and dma response transmit. offset: 08h default: 0000 0000h reference: 1394 open host controller interface specification , rev. 1.1, section 5.4 table 22. ohci version register description bit field name type description 31:25 reserved r reserved. 24 guid_rom r this field will return a 0 when read, indicating an eeprom is not present. 23:16 version r major version of the ohci. the fw322 is compliant with both version 1.0 and version 1.1 of the 1394 open host controller interface specification. this field defaults to 01h, but can be reconfigured via pci bus commands . 15:8 reserved r reserved. 7:0 revision r minor version of the ohci. the fw322 is compliant with both version 1.0 and version 1.1 of the 1394 open host controller interface specification . this field defaults to 00h, but can be reconfigured via pci bus commands . table 23. asynchronous transmit retries register description bit field name type description 31:29 secondlimit r the second limit field returns 0s when read, since outbound dual-phase retry is not implemented. 28:16 cyclelimit r the cycle limit field returns 0s when read, since outbound dual-phase retry is not implemented. 15:12 reserved r reserved. bits 15:12 return 0s when read. 11:8 maxphys respretries rw this field tells the physical response unit how many times to attempt to retry the transmit operation for the response. 7:4 maxat respretries rw this field tells the asynchronous transmit dma response unit how many times to attempt to retry the transmit operation for the response. 3:0 maxat reqretries rw this field tells the asynchronous transmit dma request unit how many times to attempt to retry the transmit operation for the response.
agere systems inc. 37 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.23 csr data register the csr data register is used to access the bus management csr registers from the host through compare-swap operations. this register contains the data to be stored in a csr if the compare is successful. offset: 0ch default: xxxx xxxxh reference: 1394 open host controller interface specification , rev. 1.1, sections 5.5.1 5.24 csr compare register the csr compare register is used to access the bus management csr registers from the host through compare- swap operations. this register contains the data to be compared with the existing value of the csr resource. offset: 10h default: xxxx xxxxh reference: 1394 open host controller interface specification , rev. 1.1, section 5.5.1 5.25 csr control register the csr control register is used to access the bus management csr registers from the host through compare- swap operations. bits in this register are used to initiate a compare-and-swap operation on a selected resource and signal when that operation is complete. offset: 14h default: 8000 000xh reference: 1394 open host controller interface specification , rev. 1.1, section 5.5.1 table 24. csr data register description bit field name type description 31:0 csrdata rwu at start of operation, the data to be stored if the compare is successful. table 25. csr compare register description bit field name type description 31:0 csrcompare rw the data to be compared with the existing value of the csr resource. table 26. csr control register description bit field name type description 31 csrdone ru this bit is set by the fw322 when a compare-swap operation is complete. it is reset whenever this register is written. 30:2 reserved r reserved. bits 30:2 return 0s when read. 1:0 csrsel rw this field selects the csr resource as follows: 00 = bus_manager_id 01 = bandwidth_available 10 = channels_available_hi 11 = channels_available_lo
38 38 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.26 configuration rom header register the configuration rom header register externally maps to the first quadlet of the 1394 configuration rom, offset 48?hffff_f000_0400. offset: 18h default: 0000 0000h reference: 1394 open host controller interface specification , rev. 1.1, section 5.5.2 5.27 bus identification register the bus identification register externally maps to the first quadlet in the bus_info_block and is addressable at ffff_f000_0404. this register is read locally at the offset specified below. offset: 1ch default: 3133 3934h reference: 1394 open host controller interface specification , rev. 1.1, section 5.5.3 table 27. configuration rom header register description bit field name type description 31:24 info_length rw ieee 1394 bus management field. must be valid when bit 17 (linken- able) of the host controller control register is set (see section 5.35). 23:16 crc_length rw ieee 1394 bus management field. must be valid when bit 17 (linken- able) of the host controller control register is set (see section 5.35). 15:0 rom_crc_value rw ieee 1394 bus management field. must be valid at any time bit 17 (linkenable) of the host controller control register is set (see section 5.35). table 28. bus identification register description bit field name type description 31?0 busid r contains the constant 32?h31333934, which is the ascii value for 1394.
agere systems inc. 39 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.28 bus options register the bus options register externally maps to the second quadlet of the bus_info_block and is 1394 addressable at ffff_f000_0408. offset: 20h default: 0000 a002h reference: 1394 open host controller interface specification , rev. 1.1, section 5.5.4 5.29 guid high register the guid high register represents the upper quadlet in a 64-bit global unique id (guid), which maps to the third quadlet in the bus_info_block 1394, addressable at ffff_f000_0410. this register contains node_vendor_id and chip_id_hi fields. this register initializes to 0s on a hardware reset, which is an illegal guid value. then the contents of this register can be loaded with a single pci write to either of two configuration registers, executed after a pci reset. the two configuration registers are located at offset 0x70, for new pci applications, and offset 0x80, for backward compatibility with fw322 05 pci applications only. after one pci configuration write has completed, this register becomes read only. offset: 24h default: 0000 0000h reference: 1394 open host controller interface specification , rev. 1.1, section 5.5.5 table 29. bus options register description bit field name type description 31:16 reserved r or rw reserved . bits return 0s when read; 23:16 and 31:27 are rw and undefined. 15:12 max_rec rw ieee 1394 bus management field. hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation. this value, max_rec_bytes, must be 512 or greater and is calculated by 2 (max_rec + 1) . software may change this field; however, this field must be valid at any time bit 17 (linkenable) of the host controller control register is set. a received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. this field is not affected by a soft reset, and defaults to value indicating 2048 bytes on a hard reset. 11:3 reserved r reserved. bits 11:3 return 0s when read. 2:0 lnk_spd r link speed. this field returns 010, indicating that the link speeds of 100 mbits/s, 200 mbits/s, and 400 mbits/s are supported. table 30. guid high register description bit field name type description 31:8 node_vendor_id rwu ieee 1394 bus management fields. firmware or hardware must ensure that this register is valid whenever hcccontrol.linkenable bit is set. 7:0 chip_id_hi rwu firmware or hardware must ensure that this register is valid when- ever hcccontrol.linkenable bit is set.
40 40 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.30 guid low register the guid low register represents the lower quadlet in a 64-bit global unique id (guid), which maps to chip_id_lo in the bus_info_block 1394, addressable at ffff_f000_0414. this register initializes to 0s on a hardware reset and behaves identically to the guid high register. the contents of this register can be loaded with a pci configura- tion write to either offset 0x74 or 0x84, as described above. offset: 28h default: 0000 0000h reference: 1394 open host controller interface specification , rev. 1.1, section 5.5.5 5.31 configuration rom mapping register the configuration rom mapping register contains the start address within system memory that maps to the start address of 1394 configuration rom for this node. offset: 34h default: 0000 0000h reference: 1394 open host controller interface specification , rev. 1.1, section 5.5.6 5.32 posted write address low register the posted write address low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. offset: 38h default: xxxx xxxxh reference: 1394 open host controller interface specification , rev. 1.1, section 13.2.8.1 table 31. guid low register description bit field name type description 31:0 chip_id_lo rw ieee 1394 bus management fields. firmware or hardware must ensure that this register is valid whenever hcccontrol.linkenable bit is set. table 32. configuration rom mapping register description bit field name type description 31:10 configromaddr rw if a quadlet read request to 1394 offset 48?hffff_f000_0400 through offset 48?hffff_f000_07ff is received, then the low- order 10 bits of the offset are added to this register to determine the host memory address of the read request. 9:0 reserved r reserved. bits 9:0 return 0s when read. table 33. posted write address low register description bit field name type description 31:0 offsetlo ru the lower 32 bits of the 1394 destination offset of the write request that was posted and failed.
agere systems inc. 41 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.33 posted write address high register the posted write address high register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. offset: 3ch default: xxxx xxxxh reference: 1394 open host controller interface specification , rev. 1.1, section 13.2.8.1 5.34 vendor id register the vendor id register holds the company id of an organization that specifies any vendor-unique registers. offset: 40h default: 0000 0000h reference: 1394 open host controller interface specification , rev. 1.1, section 5.6 table 34. posted write address high register description bit field name type description 31:16 sourceid ru this field is the bus and node number of the node that issued the write request that was posted and failed. 15:0 offsethi ru the upper 16 bits of the 1394 destination offset of the write request that was posted and failed. table 35. vendor id register description bit field name type description 31:24 vendorunique r returns 0 when read, since the fw322 does not specify any vendor unique registers. 23:0 vendorcompanyid r returns 0 when read, since the fw322 does not specify any vendor unique registers.
42 42 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.35 host controller control register the host controller control set/clear register pair provides flags for controlling the ohci portion of the fw322. offset: 50h set register 54h clear register default: x08x 0000h reference: 1394 open host controller interface specification , rev. 1.1, section 5.7 table 36. host controller control register description bit field name type description 31 bibimagevalid rsu this bit is used to enable both ohci response to block read requests to host configuration rom and the ohci mechanism for automatically updating configuration rom. when this bit is 0, the ohci returns a ack_type_error on block read requests to configu- ration rom and does not update the configrommap register or configromheader and busoptions registers when a 1394 bus reset occurs. when this bit is 1, the physical response unit handles block reads of host configuration rom and the mechanism for automatically updating configuration rom is enabled. 30 nobyteswapdata rsc this bit is used to control byte swapping during host bus accesses involving the data portion of 1394 packets. data is swapped if equal to 0, not swapped when equal to 1. 29 acktardyenable rsc this bit is used to control the acknowledgment of ack_tardy. when this bit is set to one, ack_tardy may be returned as an acknowl- edgement to configuration rom accesses from 1394 to ohci including accesses to the bus_info_block. the host controller will return ack_tardy to all other asynchronous packets addressed to the ohci node. 28:24 reserved r reserved. bits 28:24 return 0s when read. 23 programphyenable rc this bit informs upper-level software that lower-level software has consistently configured the 1394a-2000 enhancements in the link and phy core. when this bit is 1, generic software such as the ohci driver is responsible for configuring 1394a-2000 enhance- ments in the phy core and bit 22 (aphyenhanceenable) in the fw322. when this bit is 0, the generic software may not modify the 1394a-2000 enhancements in the fw322 and cannot interpret the setting of bit 22 (aphyenhanceenable). on powerup, the hardware default value will be loaded, but an alternative value may be loaded using a pci bus command. 22 aphyenhanceenable rsc when bit 23 (programphyenable) is 1 and bit 17 (linkenable) is 0, the ohci driver can set this bit to use all 1394a-2000 enhance- ments. when bit 23 (programphyenable) is set to 0, the software does not change phy enhancements or this bit. 21:20 reserved r reserved. bits 21:20 return 0s when read. 19 lps rsu link power status. this bit drives the lps signal to the phy core within the fw322 (see section 5.7 of the ohci 1.1 specification for additional details). 18 postedwriteenable rsc this bit is used to enable (1) or disable (0) posted writes. software should change this bit only when bit 17 (linkenable) is 0.
agere systems inc. 43 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.36 selfid buffer pointer register the selfid buffer pointer register points to the 2 kbyte aligned base address of the buffer in host memory where the selfid packets are stored during bus initialization. bits 31:11 are read/write accessible. offset: 64h default: xxxx xx00h reference: 1394 open host controller interface specification , rev. 1.1, section 11.1 table 36. host controller control register description (continued) bit field name type description 17 linkenable rsu this bit is cleared to 0 by either a hardware or software reset. soft- ware must set this bit to 1 when the system is ready to begin oper- ation and then force a bus reset. this bit is necessary to keep other nodes from sending transactions before the local system is ready. when this bit is cleared, the fw322 is logically and immediately disconnected from the 1394 bus, no packets are received or processed, and no packets transmitted. 16 softreset rsu when this bit is set, all fw322 states are reset, all fifos are flushed, and all ohci registers are set to their hardware reset values unless otherwise specified. pci registers are not affected by this bit. this bit remains set while the softreset is in progress and reverts back to 0 when the reset has completed. 15:0 reserved r reserved. bits 15:0 return 0s when read. table 37. selfid buffer pointer register description bit field name type description 31:11 selfidbufferptr rw contains the 2 kbyte aligned base address of the buffer in host memory where received selfid packets are stored. 10:0 reserved r reserved.
44 44 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.37 selfid count register the selfid count register keeps a count of the number of times the selfid process has occurred. the register also flags any selfid errors and maintains a count of the amount of selfid data in the selfid buffer. offset: 68h default: x0xx 0000h reference: 1394 open host controller interface specification , rev. 1.1, section 11.2 5.38 isochronous receive multiple channel mask high (irmultichanmaskhi) register the isochronous receive multiple channel mask high set/clear register is used to enable packet receives from the upper 32 isochronous data channels. a read from either the set register or clear register returns the content of the isochronous receive multiple channel mask high register. offset: 70h set register 74h clear register default: xxxx xxxxh reference: 1394 open host controller interface specification , rev. 1.1, section 10.4.1.1 table 38. selfid count register description bit field name type description 31 selfiderror ru when this bit is 1, an error was detected during the most recent selfid packet reception. the contents of the selfid buffer are undefined. this bit is cleared after a selfid reception in which no errors are detected. note that an error can be a hardware error or a host bus write error. 30:24 reserved r reserved. bits 30:24 return 0s when read. 23:16 selfidgeneration ru the value in this field increments each time a bus reset is detected. this field rolls over to 0 after reaching 255. 15:11 reserved r reserved. bits 15:11 return 0s when read. 10:2 selfidsize ru this field indicates the number of quadlets that have been written into the selfid buffer for the current bits 23:16 (selfidgeneration field). this includes the header quadlet and the selfid data. this field is cleared to 0 when the selfid reception begins. 1:0 reserved r reserved. bits 1:0 return 0s when read. table 39. isochronous receive channel mask high register description bit field name type description 31:0 isochannel(n + 32) rsc if bit n (where n = a bit number 0?31) is set, iso channel number (n + 32) is enabled.
agere systems inc. 45 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.39 isochronous receive multiple channel mask low (irmultichanmasklo) register the isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32 isochronous data channels. offset: 78h set register 7ch clear register default: xxxx xxxxh reference: 1394 open host controller interface specification , rev. 1.1, section 10.4.1 table 40. isochronous receive channel mask low register description bit field name type description 31:0 isochannel n rsc if bit n (where n = a bit number 0?31) is set, iso channel number n is enabled.
46 46 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.40 interrupt event (intevent) register the interrupt event set/clear register reflects the state of the various fw322 interrupt sources. the interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. reading the inteventset register returns the current state of the intevent register. reading the intevent- clear register returns the masked version of the intevent register (i.e., the bit-wise and function of intevent and intmask). offset: 80h set register 84h clear register default: xxxx 0xxxh reference: 1394 open host controller interface specification , rev. 1.1, section 6.1 table 41. interrupt event register description bit field name type description 31 reserved r reserved. bit 31 returns 0 when read. 30 vendorspecific rscu this vendor-specific interrupt event is reported when serial eeprom read is complete. note: this bit should always be reset, since there is no eeprom. 29 softinterrupt rsc soft interrupt. this bit may be used by software to generate a host controller interrupt for its own use. 28 reserved r reserved. bit 28 returns 0 when read. 27 ack_tardy rscu this bit will be set when the acktardyenable bit of the hc control register (see section 5.35) is set to 1 and any of the following conditions occur: a. data is present in a fifo that is to be delivered to the host. b. the physical response unit is busy processing requests or sending responses. c. the host controller sent an ack_tardy acknowledgment. 26 phyregrcvd rscu the fw322 has received a phy core register data byte, which can be read from the phy core layer control register. 25 cycletoolong rscu if bit 21 (cyclemaster) of the link control register (see table 47) is set, then this indicates that over 125 s have elapsed between the start of sending a cycle start packet and the end of a subaction gap. the link control register bit 21 (cyclemaster) is cleared by this event. 24 unrecoverableerror rscu this event occurs when the fw322 encounters any error that forces it to stop operations on any or all of its subunits, for example, when a dma context sets its dead bit. while this bit is set, all normal interrupts for the context(s) that caused this interrupt are blocked from being set. 23 cycleinconsistent rscu a cycle start was received that had values for cycleseconds and cyclecount fields that are different from the values in bits 31:25 (cycle- seconds field) and bits 24:12 (cyclecount field) of the isochronous cycle timer register (see table 50 ). 22 cyclelost rscu a lost cycle is indicated when no cycle_start packet is sent/received between two successive cyclesynch events. a lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cyclesynch event or if an arbitration reset gap is detected after a cyclesynch event without an intervening cycle start. this bit may be set either when it occurs or when logic predicts that it will occur.
agere systems inc. 47 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) table 41. interrupt event register description (continued) bit field name type description 21 cycle64seconds rscu this bit indicates that the seventh bit of the cycleseconds (see table 50 ) counter has changed. 20 cyclesynch rscu this bit indicates that a new isochronous cycle has started. this bit is set when the low-order bit of the cyclecount (see table 50 ) toggles. 19 phy rscu this bit indicates the phy core requests an interrupt through a status transfer. 18 regaccessfail rscu this bit indicates that an ohci register access failed due to a missing sclk clock signal from the phy. when a register access fails, this bit will be set before the next register access. 17 busreset rscu this bit indicates that the phy core chip has entered bus reset mode. 16 selfidcomplete rscu a selfid packet stream has been received. it is generated at the end of the bus initialization process. this bit is turned off simultaneously when bit 17 (busreset) is turned on. 15 selfidcomplete2 rscu secondary indication of the end of a selfid packet stream. this bit will be set by the ohci when it sets selfidcomplete, and will retain state independent of the busreset bit of this register. 14:10 reserved r reserved. bits 14:10 return 0s when read. 9 lockresperr rscu this bit indicates that the fw322 sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. 8 postedwriteerr rscu this bit indicates that a host bus error occurred while the fw322 was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. 7 isochrx ru isochronous receive dma interrupt. this bit indicates that one or more isochronous receive contexts have generated an interrupt. this is not a latched event; it is the or ing of all bits in the isochronous receive interrupt event and isochronous receive interrupt mask registers. the isochronous receive interrupt event register (see table 45 ) indicates which contexts have interrupted. 6 isochtx ru isochronous transmit dma interrupt. this bit indicates that one or more isochronous transmit contexts have generated an interrupt. this is not a latched event; it is the or ing of all bits in the isochronous transmit interrupt event register (see table 43) and isochronous transmit inter- rupt mask (see table 44) register. the isochronous transmit interrupt event register indicates which contexts have interrupted. 5 rspkt rscu this bit indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor?s xferstatus and rescount fields have been updated. 4 rqpkt rscu this bit indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor?s xferstatus and rescount fields have been updated. 3 arrs rscu asynchronous receive response dma interrupt. this bit is condi- tionally set upon completion of an arrs dma context command descriptor. 2 arrq rscu asynchronous receive request dma interrupt. this bit is condition- ally set upon completion of an arrq dma context command descriptor. 1 resptxcomplete rscu asynchronous response transmit dma interrupt. this bit is condi- tionally set upon completion of an atrs dma command. 0 reqtxcomplete rscu asynchronous request transmit dma interrupt. this bit is condi- tionally set upon completion of an atrq dma command.
48 48 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.41 interrupt mask (intmask) register the interrupt mask set/clear register is used to enable/disable the various fw322 interrupt sources. reads from either the set register or the clear register always return the contents of the interrupt mask register. in all cases except masterintenable (bit 31), the enables for each interrupt event align with the interrupt event (intevent) regis- ter bits (see table 41). a one bit in the intmask register enables the corresponding intevent register bit to generate a processor interrupt. a zero bit in intmask disables the corresponding intevent register bit from generating a pro- cessor interrupt. a bit is set in the intmask register by writing a one to the corresponding bit in the intmaskset address and cleared by writing a one to the corresponding bit in the intmaskclear address. offset: 88h set register 8ch clear register default: xxxx 0xxxh reference: 1394 open host controller interface specification , rev. 1.1, section 6.2 table 42. interrupt mask register description bit field name type description 31 masterintenable rscu master interrupt enable. if this bit is set, then external interrupts are generated in accordance with the interrupt mask register. if this bit is cleared, then external interrupts are not generated, regardless of the interrupt mask register settings. the value of masterintenable has no effect on the value returned by reading the inteventclear. 30 vendorspecific rsc when this bit is set, this vendor-specific interrupt mask enables interrupt generation when bit 30 (vendorspecific) of the interrupt event register (table 41) is set. 29 softinterrupt rsc soft interrupt. this bit may be used by software to generate a host controller interrupt for its own use. when set, this bit enables the corresponding intevent register bit to generate a processor interrupt. 28 reserved r reserved. bit 28 returns 0 when read. 27 ack_tardy rscu a one bit enables the corresponding intevent register bit to generate a processor interrupt. a zero bit disables the corresponding intevent register bit from generating a processor interrupt. 26 phyregrcvd 25 cycletoolong 24 unrecoverableerror 23 cycleinconsistent 22 cyclelost 21 cycle64seconds 20 cyclesynch 19 phy 18 regaccessfail 17 busreset 16 selfidcomplete 15 selfidcomplete2 14:10 reserved r reserved. bits 14:10 return 0s when read. 9 lockresperr rscu when set, these bits enable the corresponding intevent register bits to generate a processor interrupt. 8 postedwriteerr 7 isochrx 6 isochtx 5 rspkt 4 rqpkt 3 arrs 2 arrq 1 resptxcomplete 0 reqtxcomplete
agere systems inc. 49 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.42 i sochronous transmit interrupt event (isoxmitintmask) register the isochronous transmit interrupt event (isoxmitintmask) set/clear register reflects the interrupt state of the isoch- ronous transmit contexts. an interrupt is generated on behalf of an isochronous transmit context if an output_last command completes and its interrupt bits are set. upon determining that the interrupt event regis- ter isochtx (bit 6) (see table 41) interrupt has occurred, software can check this register to determine which con- text(s) caused the interrupt. the interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. reading the isoxmitinteventset register returns the current state of the isoxmitintevent register. reading the isoxmitinteventclear register returns the masked version of the isoxmitintevent register (i.e., the bit-wise and function of isoxmitintevent and isoxmitintmask ). offset: 90h set register 94h clear register default: 0000 00xxh reference: 1394 open host controller specification , rev. 1.1, section 6.3 table 43. isochronous transmit interrupt event register description bit field name type description 31:8 reserved r reserved. bits 31:8 return 0s when read. 7 isoxmit7 rscu isochronous transmit channel 7 caused the interrupt event register bit 6 (isochtx) interrupt. 6 isoxmit6 rscu isochronous transmit channel 6 caused the interrupt event register bit 6 (isochtx) interrupt. 5 isoxmit5 rscu isochronous transmit channel 5 caused the interrupt event register bit 6 (isochtx) interrupt. 4 isoxmit4 rscu isochronous transmit channel 4 caused the interrupt event register bit 6 (isochtx) interrupt. 3 isoxmit3 rscu isochronous transmit channel 3 caused the interrupt event register bit 6 (isochtx) interrupt. 2 isoxmit2 rscu isochronous transmit channel 2 caused the interrupt event register bit 6 (isochtx) interrupt. 1 isoxmit1 rscu isochronous transmit channel 1 caused the interrupt event register bit 6 (isochtx) interrupt. 0 isoxmit0 rscu isochronous transmit channel 0 caused the interrupt event register bit 6 (isochtx) interrupt.
50 50 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.43 isochronous transmit interrupt mask (isoxmitintmask) register the isochronous transmit interrupt mask set/clear register is used to enable the isochtx interrupt source on a per- channel basis. reads from either the set register or the clear register, always return the contents of the isochro- nous transmit interrupt mask register. in all cases, the enables for each interrupt event align with the event register bits detailed in table 41. offset: 98h set register 9ch clear register (returns isoxmitevent and isoxmitmask when read) default: 0000 00xxh reference: 1394 open host controller specification , rev. 1.1, section 6.3 table 44. isochronous transmit interrupt event description bit field name type description 31:8 reserved r reserved. bits 31:8 return 0s when read. 7:0 isoxmit7:isoxmit0 rscu setting one of these bits enables the corresponding interrupt event in the isoxmitintevent register. clearing a bit in this register disables the corresponding interrupt event in the isoxmitintevent register.
agere systems inc. 51 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.44 isochronous receive interrupt event (isorecvintevent) register the isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. an interrupt is generated on behalf of an isochronous receive context if an input_* command completes and its interrupt bits are set. upon determining that the interrupt event register isochrx (bit 7) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. the interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear reg- ister. the isorecvintmask register is anded with the isorecvintevent register to enable selected bits to generate pro- cessor interrupts. reading the isorecvinteventset register returns the current state of the isorecvintevent regis- ter. reading isorecvinteventclear register returns the masked version of the isorecvintevent register (i.e., the bit-wise and function of isorecvtintevent and isorecvtintmask ). offset: a0h set register a4h clear register default: 0000 0000h reference: 1394 open host controller specification , rev. 1.1, section 6.4 table 45. isochronous receive interrupt event description bit field name type description 31:8 reserved r reserved. bits 31:8 return 0s when read. 7 isorecv7 rscu isochronous receive context 7 caused the interrupt event register bit 7 (isochrx) interrupt. 6 isorecv6 rscu isochronous receive context 6 caused the interrupt event register bit 7 (isochrx) interrupt. 5 isorecv5 rscu isochronous receive context 5 caused the interrupt event register bit 7 (isochrx) interrupt. 4 isorecv4 rscu isochronous receive context 4 caused the interrupt event register bit 7 (isochrx) interrupt. 3 isorecv3 rscu isochronous receive context 3 caused the interrupt event register bit 7 (isochrx) interrupt. 2 isorecv2 rscu isochronous receive context 2 caused the interrupt event register bit 7 (isochrx) interrupt. 1 isorecv1 rscu isochronous receive context 1 caused the interrupt event register bit 7 (isochrx) interrupt. 0 isorecv0 rscu isochronous receive context 0 caused the interrupt event register bit 7 (isochrx) interrupt.
52 52 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.45 isochronous receive interrupt mask (isorecvintmask) register the isochronous receive interrupt mask set/clear register is used to enable the isochrx interrupt source on a per- channel basis. reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. in all cases, the enables for each interrupt event correspond to the isorecvintevent register bits. setting a bit in this register enables the corresponding interrupt event in the isorecvintevent register. clearing a bit in this register disables the corresponding interrupt event in the isorecvintevent register. offset: a8h set register ach clear register default: 0000 000xh reference: 1394 open host controller specification , rev. 1.1, section 6.4 5.46 fairness control register the fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval, as specified by the ieee-1394a specification . offset: dch default: 0000 0000h reference: 1394 open host controller specification , rev. 1.1, section 5.9 table 46. fairness control register description bit field name type description 31:8 reserved r reserved. bits 31:8 return 0s when read. 7:0 pri_req rw this field specifies the maximum number of priority arbitration requests for asynchro- nous request packets that the link is permitted to make of the phy core during the fairness interval.
agere systems inc. 53 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.47 link control register the link control register provides flags to enable and configure the link core cycle timer and receiver portions of the fw322. offset: e0h set register e4h clear register default: 00x0 0x00h reference: 1394 open host controller specification , rev. 1.1, section 5.10 table 47. link control register description bit field name type description 31:23 reserved r reserved. bits 31:23 return 0s when read. 22 cyclesource rsc this bit is set to 0, since the fw322 does not support an external cycle timer. 21 cyclemaster rscu when this bit is set, and the fw322 phy core has notified the ohci core that it is root, the ohci generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22. when this bit is cleared, the ohci accepts received cycle start packets to maintain synchronization with the node that is sending them. this bit is automatically reset when bit 25 (cycletoolong) of the interrupt event register (see table 41) is set and cannot be set until bit 25 (cycletoolong) is cleared. 20 cycletimerenable rsc when this bit is set, the cycle timer offset counts cycles of the 24.576 mhz clock and rolls over at the appropriate time based on the settings of the above bits. when this bit is cleared, the cycle timer offset does not count. 19:11 reserved r reserved. bits 19:11 return 0s when read. 10 rcvphypkt rsc when this bit is set, the receiver accepts incoming phy core packets into the ar request context if the ar request context is enabled. this does not control receipt of self-identification packets received outside of the selfid phase of bus initialization. 9 rcvselfid rsc when this bit is set, the receiver accepts incoming self-identifica- tion packets. before setting this bit to 1, software must ensure that the selfid buffer pointer register contains a valid address. 8:7 reserved r reserved. 6 tag1syncfilterlock rs when this bit is set, the tag1syncfilter bit of the ir context match register (see table 61) equals one for all ir contexts. when this bit is cleared, the tag1synchfilter bit has read/write access. a hard- ware reset clears this bit to 0. a soft reset has no effect. 5:0 reserved r reserved. bits 5:0 return 0s when read.
54 54 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.48 node identification register the node identification register contains the address of the node on which the ohci resides, and indicates the valid node number status. the 16-bit combination of the busnumber field (bits 15:6) and the nodenumber field (bits 5:0) is referred to as the node id. offset: e8h default: 0000 ffxxh reference: 1394 open host controller specification , rev. 1.1, section 5.11 table 48. node identification register description bit field name type description 31 idvalid ru this bit indicates whether or not the fw322 has a valid node number. it is cleared when a 1394 bus reset is detected and set when the fw322 receives a new node number from the phy core. 30 root ru this bit is set during the bus reset process if the attached phy core is root. 29:28 reserved r reserved. bits 29:28 return 0s when read. 27 cps ru set if the phy core is reporting that cable power status is ok. 26:16 reserved r reserved. bits 26:16 return 0s when read. 15:6 busnumber rwu this number is used to identify the specific 1394 bus to which the fw322 belongs when multiple 1394-compatible buses are connected via a bridge. 5:0 nodenumber ru this number is the physical node number established by the phy core during self-identification. it is automatically set to the value received from the phy core after the self-identification phase. if the phy core sets the nodenumber to 63, then software should not set the run bit of the context control register for either of the at dma contexts (see table 55).
agere systems inc. 55 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.49 phy core layer control register the phy core layer control register is used to read or write a phy core register. offset: ech default: 0000 0000h reference: 1394 open host controller specification , rev. 1.1, section 5.12 5.50 isochronous cycle timer register the isochronous cycle timer register indicates the current cycle number and offset. when the fw322 is cycle mas- ter, this register is transmitted with the cycle start message. when the fw322 is not cycle master, this register is loaded with the data field in an incoming cycle start. in the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. offset: f0h default: xxxx xxxxh reference: 1394 open host controller specification , rev. 1.1, section 5.13 table 49. phy core layer control register description bit field name type description 31 rddone ru this bit is cleared to 0 by the fw322 when either bit 15 (rdreg) or bit 14 (wrreg) is set. this bit is set when a register transfer is received by the ohci core from the phy core and rddata is updated. 30:28 reserved r reserved. bits 30:28 return 0s when read. 27:24 rdaddr ru this is the address of the register most recently received from the phy core. 23:16 rddata ru this field is the contents of a phy core register, which have been read at rdaddr. 15 rdreg rwu this bit is set by software to initiate a read request to a phy core register and is cleared by hardware when the request has been sent. bit 14 (wrreg) must not be set when bit 15 (rdreg) is set. 14 wrreg rwu this bit is set by software to initiate a write request to a phy core register and is cleared by hardware when the request has been sent. bit 15 (rdreg) must not be set when bit 14 (wrreg) is set. 13:12 reserved r reserved. bits 13:12 return 0s when read. 11:8 regaddr rw this field is the address of the phy core register to be written or read. 7:0 wrdata rw this field is the data to be written to a phy core register and is ignored for reads. table 50. isochronous cycle timer register description bit field name type description 31:25 cycleseconds rwu this field counts seconds [rollovers from bits 24:12 (cyclecount field)] modulo 128. 24:12 cyclecount rwu this field counts cycles [rollovers from bits 11:0 (cycleoffset field)] modulo 8000. 11:0 cycleoffset rwu this field counts 24.576 mhz clocks modulo 3072 (i.e., 125 ms). if an external 8 khz clock configuration is being used, then this bit must be set to 0 at each tick of the external clock.
56 56 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.51 asynchronous request filter high register the asynchronous request filter high set/clear register is used to enable asynchronous receive requests on a per- node basis, and handles the upper node ids. when a packet is destined for either the physical request context or the arrq context, the source node id is examined. if the bit corresponding to the node id is not set in this register, then the packet is not acknowledged and the request is not queued. the node id comparison is done if the source node is on the same bus as the fw322. all nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set. offset: 100h set register 104h clear register default: 0000 0000h reference: 1394 open host controller specificatio n, rev. 1.1, section 5.14 5.52 asynchronous request filter low register the asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per- node basis, and handles the lower-node ids. other than filtering different node ids, this register behaves identi- cally to the asynchronous request filter high register. offset: 108h set register 10ch clear register default: 0000 0000h reference: 1394 open host controller specification , rev. 1.1, section 5.14 table 51. asynchronous request filter high register description bit field name type description 31 asynreqresourceall rscu if this bit is set, then all asynchronous requests received by the fw322 from nonlocal bus nodes are accepted and the values of all asynreqresourcen bits will be ignored. set/clear operations to this register while the intevent.busreset bit (see table 41) is asserted will have no effect. a bus reset will not affect the value of the asynreqresourceall bit. 30:0 asynreqresourcen rscu if this bit is set, then asynchronous requests received from node n (where n = the bit number + 32) on local bus are accepted by fw322. all asyn- reqresourcen bits will be cleared to zero when a bus reset occurs. set/ clear operations to this register while the intevent.busreset bit (see table 41) is asserted will have no effect. table 52. asynchronous request filter low register description bit field name type description 31:0 asynreqresourcen rscu if this bit is set for local bus node number n (where n = the bit number from 0 to 31), then asynchronous requests received by the fw322 from that node are accepted. all asynreqresourcen bits will be cleared to zero when a bus reset occurs. set/clear operations to this register while the intevent.busreset bit (see table 41) is asserted will have no effect.
agere systems inc. 57 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.53 physical request filter high register the physical request filter high set/clear register is used to enable physical receive requests on a per-node basis and handle the upper-node ids. when a packet is destined for the physical request context and the node id has been compared against the arrq registers, then the comparison is done again with this register. if the bit corre- sponding to the node id is not set in this register, then the request is handled by the arrq context instead of the physical request context. offset: 110h set register 114h clear register default: 0000 0000h reference: 1394 open host controller specification , rev. 1.1, section 5.14.2 5.54 physical request filter low register the physical request filter low set/clear register is used to enable physical receive requests on a per-node basis and handle the lower-node ids. when a packet is destined for the physical request context and the node id has been compared against the asynchronous request filter registers, then the node id comparison is done again with this register. if the bit corresponding to the node id is not set in this register, then the request is handled by the asynchronous request context instead of the physical request context. offset: 118h set register 11ch clear register default: 0000 0000h reference: 1394 open host controller specification , rev. 1.1, section 5.14.2 table 53. physical request filter high register description bit field name type description 31 physreqresourceallbuses rsc if this bit is set, then all asynchronous requests received by the fw322 from nonlocal bus nodes are accepted. set/clear operations to this register while the intevent.busreset bit (see table 41) is asserted will have no effect. a bus reset will not affect the value of the physreqre- sourceallbuses bit. 30:0 physreqresourcen rsc if this bit is set, requests received by the fw322 from local bus node n (where n = bit number + 32) will be handled through the physical request context. set/clear operations to this register while the intevent.busreset bit (see table 41) is asserted will have no effect. all physreqresourcen bits will be cleared to zero when a bus reset occurs. table 54. physical request filter low register description bit field name type description 31:0 physreqresourcen rsc if this bit is set, requests received by the fw322 from local bus node n (where n = bit number) will be handled through the physical request context. set/clear operations to this register while the intevent.busreset bit (see table 41) is asserted will have no effect. all physreqresourcen bits will be cleared to zero when a bus reset occurs.
58 58 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.55 asynchronous context control register the asynchronous context control set/clear register controls the state and indicates status of the dma context. offset: 180h set register (atrq) 184h clear register (atrq) 1a0h set register (atrs) 1a4h clear register (atrs) 1c0h set register (arrq) 1c4h clear register (arrq) 1e0h set register (arrs) 1e4h clear register (arrs) default: 0000 x0xxh reference: 1394 open host controller specification , rev. 1.1, section 7.22, 8.3.2, 3.1.1 table 55. asynchronous context control register description bit field name type description 31:16 reserved r reserved. bits 31:16 return 0s when read. 15 run rscu this bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the fw322 changes this bit (i.e., sets it to 0) only on a hardware or software reset. 14:13 reserved r reserved. bits 14:13 return 0s when read. 12 wake rsu software sets this bit to cause the fw322 to continue or resume descriptor processing. the fw322 clears this bit on every descriptor fetch. 11 dead ru the fw322 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). 10 active ru the fw322 sets this bit to 1 when it is processing descriptors. 9:8 reserved r reserved. bits 9:8 return 0s when read. 7:5 spd note: these bits are reserved, unde- fined for the atrq and atrs contexts. ru this field indicates the speed at which a packet was received or trans- mitted, and only contains meaningful information for receive contexts. this field is encoded as follows: 000 = 100 mbits/s. 001 = 200 mbits/s. 010 = 400 mbits/s. 011 = 800 mbits/s. all other values are reserved. software should not attempt to interpret the contents of this field while the active or wake bits are set. 4:0 eventcode ru this field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully.
agere systems inc. 59 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.56 asynchronous context command pointer register the asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the fw322 accesses when software enables the context by setting the asynchronous context control register bit 15 (run). offset: 18ch (atrq) 1ach (atrs) 1cch (arrq) 1ech (arrs) default: xxxx xxxxh reference: 1394 open host controller specification , rev. 1.1, sections 3.1.2, 7.2.1, 8.3.1 table 56. asynchronous context command pointer register description bit field name type description 31:4 descriptoraddress rwu contains the upper 28 bits of the address of a 16-byte aligned descriptor block. 3:0 z rwu these bits indicate the number of contiguous descriptors at the address pointed to by the descriptor address. if z is 0, then it indicates that the descriptoraddress field (bits 31:4) is not valid. valid values for z are context specific. refer to the ohci specification for more details.
60 60 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.57 isochronous transmit context control (it dma contextcontrol) register the isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit dma contexts. the n value in the following register addresses indicates the context number (n = 0:7). offset: 200h + (16 x n) set register 204h + (16 x n) clear register default: xxxx x0xxh reference: 1394 open host controller specification , rev. 1.1, sections 9.2, 3.1.1 table 57. isochronous transmit context control register description bit field name type description 31 cyclematchenable rscu when this bit is set to 1, processing occurs such that the packet described by the context?s first descriptor block is transmitted in the cycle whose number is specified in the cyclematch field (bits 30:16). the cyclematch field (bits 30:16) must match the low-order 2 bits of cycleseconds and the 13-bit cyclecount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. since the isochronous transmit dma controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted. the effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 open host controller inter- face specification . once the context has become active, hardware clears this bit. 30:16 cyclematch rsc contains a 15-bit value, corresponding to the low-order 2 bits of the bus isochronous cycle time register cycleseconds field (bits 31:25) and the cyclecount field (bits 24:12) (see table 50). if bit 31 (cyclematch- enable) is set, then this isochronous transmit dma context becomes enabled for transmits when the low-order 2 bits of the bus isochronous cycle timer register cycleseconds field (bits 31:25) and the cyclecount field (bits 24:12) value equal this field?s (cyclematch) value. 15 run rscu this bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the fw322 changes this bit only on a hardware or software reset. 14:13 reserved r reserved. bits 14:13 return 0s when read. 12 wake rsu software sets this bit to cause the fw322 to continue or resume descriptor processing. the fw322 clears this bit on every descriptor fetch. 11 dead ru the fw322 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). 10 active ru the fw322 sets this bit to 1 when it is processing descriptors. 9:5 reserved r reserved. bits 9:5 return 0s when read. 4:0 event code ru following an output_last* command, the error code is indicated in this field. possible values are ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
agere systems inc. 61 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.58 isochronous transmit context command pointer register the isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the fw322 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register bit 15 (run). the n value in the following register addresses indicates the context number (n = 0:7). offset: 20ch + (16 x n) default: xxxx xxxxh reference: 1394 open host controller specification , rev. 1.1, sections 9.2.1, 3.1.2 5.59 isochronous receive context control (ir dma contextcontrol) register the isochronous receive context control set/clear register controls options, state, and status for the isochronous receive dma contexts. the n value in the following register addresses indicates the context number (n = 0:7). offset: 400h + (32 x n) set register 404h + (32 x n) clear register default: x000 x0xxh reference: 1394 open host controller specification , rev. 1.1, sections 10.3, 3.1.2 table 58. isochronous transmit context command pointer register description bit field name type description 31:4 descriptoraddress rwu address of the context program, which will be executed when a dma context is started. all descriptors are 16-byte aligned, so the four least significant bits of any descriptor address must be zero. 3:0 z rwu these bits indicate how many physically contiguous descriptors are pointed to by descriptoraddress. table 59. isochronous receive context control register description bit field name type description 31 bufferfill rsc when this bit is set, received packets are placed back-to-back to com- pletely fill each receive buffer. when this bit is cleared, each received packet is placed in a single buffer. if bit 28 (multichanmode) is set to 1, then this bit must also be set to 1. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. 30 isochheader rsc when this bit is 1, received isochronous packets include the complete 4-byte isochronous packet header seen by the link layer. the end of the packet is marked with an xferstatus in the first doublet, and a 16-bit timestamp indicating the time of the most recently received (or sent) cyclestart packet. when this bit is cleared, the packet header is stripped off of received isochronous packets. the packet header, if received, immediately precedes the packet payload. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. 29 cyclematchenable rscu when this bit is set, the context begins running only when the 15-bit cyclematch field (bits 26:12) in the ircontext match register (see table 61) matches the two low-order bits of the cycleseconds field and the 13-bit cyclecount field in the cycle timer register. the effects of this bit, however, are impacted by the values of other bits in this register. once the context has become active, hardware clears this bit. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set.
62 62 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) table 59. isochronous receive context control register description (continued) bit field name type description 28 multichanmode rsc when this bit is set, the corresponding isochronous receive dma con- text receives packets for all isochronous channels enabled in the isoch- ronous receive channel mask high and isochronous receive channel mask low registers. the isochronous channel number specified in the isochronous receive dma context match register is ignored. when this bit is cleared, the isochronous receive dma context receives packets for the channel number specified in the context match register. only one isochronous receive dma context may use the isochronous receive channel mask registers. if more than one isochronous receive context control register has this bit set, then results are undefined. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 27 dualbuffermode rsc when this bit is set, received packets are separated into first and sec- ond payload and streamed independently to the first buffer series and second buffer series (see ohci v.1.1, 10.2.3). both multichanmode and buffer fill must be programmed to zero when this bit is set. the value of dualbuffermode will not be changed while active or run is set. 26:16 reserved r reserved. bits 26:16 return 0s when read. 15 run rscu this bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the fw322 changes this bit only on a hardware or software reset. 14:13 reserved r reserved. bits 14:13 return 0s when read. 12 wake rsu software sets this bit to cause the fw322 to continue or resume descriptor processing. the fw322 clears this bit on every descriptor fetch. 11 dead ru the fw322 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). 10 active ru the fw322 sets this bit to 1 when it is processing descriptors. 9:8 reserved r reserved. bits 9:8 return 0s when read. 7:5 spd ru this field indicates the speed at which the packet was received. 000 = 100 mbits/s. 001 = 200 mbits/s. 010 = 400 mbits/s. 011 = 800 mbits/s. all other values are reserved. 4:0 event code ru following an input_* command, the error or status code is indicated in this field (see ohci v.1.1, section 10.3.2 and table 3-2).
agere systems inc. 63 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.60 isochronous receive context command pointer register the isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the fw322 accesses when software enables an isochronous receive context by setting the isochronous receive context control register bit 15 (run). the n value in the following register addresses indicates the context number (n = 0:7). offset: 40ch + (32 x n) default: xxxx xxxxh reference: 1394 open host controller specification , rev. 1.1, sections 10.3, 3.1.2 table 60. isochronous receive context command pointer register description bit field name type description 31:4 descriptoraddress rwu address of the context program that will be executed when a dma con- text is started. 3:0 z rwu these bits indicate how many physically contiguous descriptors are pointed to by descriptor address. in buffer full mode, z will be either one or zero. in packet-per-buffer mode, z will be from zero to eight.
64 64 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.61 isochronous receive context match (ir dma contextmatch) register the isochronous receive context match register is used to control on which isochronous cycle the context should start. the register is also used to control which packets are accepted by the context. offset: 410ch + (32 x n) default: xxxx xxxxh reference: 1394 open host controller specification , rev. 1.1, section 10.3. 3 table 61. isochronous receive context match register description bit field name type description 31 tag3 rw if this bit is set, then this context matches on iso receive packets with a tag field of 11b. 30 tag2 rw if this bit is set, then this context matches on iso receive packets with a tag field of 10b. 29 tag1 rw if this bit is set, then this context matches on iso receive packets with a tag field of 01b. 28 tag0 rw if this bit is set, then this context matches on iso receive packets with a tag field of 00b. 27 reserved r reserved. bit 27 returns a 0 when read. 26:12 cyclematch rw contains a 15-bit value, corresponding to the low-order 2 bits of cycle- seconds and the 13-bit cyclecount field in the cyclestart packet. if iso- chronous receive context control register bit 29 (cyclematchenable) is set, then this context is enabled for receives when the two low-order bits of the bus isochronous cycle timer register cycleseconds field (bits 31:25) and cyclecount field (bits 24:12) value equal this field?s (cyclem- atch) value. 11:8 sync rw this field contains the 4-bit field, which is compared to the sync field of each isochronous packet for this channel when the command descrip- tor?s w field is set to 11b. 7 reserved r reserved. bit 7 returns 0 when read. 6 tag1syncfilter rw if this bit and bit 29 (tag1) are set, then packets with tag2?b01 are accepted into the context if the two most significant bits of the packets sync field are 00b. packets with tag values other than 01b are filtered according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively) without any additional restrictions. if this bit is cleared, then this context matches on isochronous receive packets as specified in bits 28:31 (tag0:tag3) with no additional restrictions. if the tag1syncfilterlock bit of the link control register is set, then this bit is read only and is set to one by the ohci. 5:0 channelnumber rw this 6-bit field indicates the isochronous channel number for which this isochronous receive dma context accepts packets.
agere systems inc. 65 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.62 fw322 vendor-specific registers the fw322 contains a number of vendor-defined registers used for diagnostics and control of low-level hardware functionality. these registers are addressable in the upper 2k of the 4k region defined by pci base address register 0 (registers defined by the ohci specification reside in the lower 2k of this region). on powerup, the hard- ware default value will be loaded, but an alternative value may be loaded using a pci bus command. these control registers should not be changed when the link is enabled. 5.63 isochronous dma control the fields in this register control when the isochronous dma engines access the pci bus and how much data they will attempt to move in a single pci transaction. the actual pci burst sizes will also be affected by 1394 packet size, host memory buffer size, fifo constraints, and the pci cache line size. offset: 800h default: 0000 7373h table 62. fw322 vendor-specific registers description offset register name description 12?h800 isodmactrl controls pci access for the isochronous dma engines. initial values are loaded from hardware defaults (see table 63 ). 12?h808 asydmactrl controls pci access and at fifo threshold for the asynchronous dma engines. initial values are loaded from hardware defaults (see table 63 ). 12?h840 linkoptions controls low-level func tionality of the link core. initia l values are loaded from hard- ware defaults (see table 63 ). table 63. isochronous dma control registers description bits field description 15:12 it maximum burst the maximum number of quadlets that will be fetched by the it dma in one pci transaction. the maximum burst is 16 x (n + 1) quadlets; n defaults to 7 (128 quadlets). max value of n is 0xf. 11:8 it threshold this field defines the amount of available space that is needed in the it fifo, before the it dma will request access to the pci bus. the threshold is 16 x (n + 1) quadlets; n defaults to 3 (64 quadlets). note, however, that the it dma may request access to the pci bus sooner if the amount of data to be fetched from memory is less than the amount of space available in the it fifo. max value of n is 0xf. 7:4 ir maximum burst the maximum number of quadlets that will be written by the ir dma in one pci transaction. the maximum burst is 16 x (n + 1) quadlets; n defaults to 7 (128 quadlets). max value of n is 0xf. 3:0 ir threshold this field defines the amount of available data that is needed in the ir fifo, before the ir dma will request access to the pci bus. the threshold is 16 x (n + 1) quadlets; n defaults to 0 (16 quadlets). note, however, that the ir dma may request access to the pci bus sooner if the amount of data available in the fifo exceeds the space remaining in the current host memory buffer or a complete packet resides in the fifo. max value of n is 0xf.
66 66 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 5 internal registers (continued) 5.64 asynchronous dma control the fields in this register control the functionality within the asynchronous and physical dma engines. accesses to the pci bus and how much data the dma engines will attempt to move in a single pci transaction can be con- trolled. the actual pci burst sizes will also be affected by 1394 packet size, host memory buffer size, fifo con- straints, and the pci cache line size. offset: 808h default: 0010 7373h table 64. asynchronous dma control registers description bits field description 24 retry threshold maximum enable when this bit is set, a packet being retried (e.g., due to an ack_busy on the initial attempt) will behave as if the at fifo threshold value was set to the maximum (n = 0x20). the purpose of this feature is to prevent a packet that previously experienced a fifo underrun on the initial transmit attempt from failing again due to a fifo underrun on the retry attempt. if this bit is not set, retried packets will use the same at fifo threshold as the initial transmit attempt. the default value of this field is 0x0. 23:16 at fifo threshold this field defines the number of quadlets of packet data that must be available in the at fifo before the link will be notified that there is an asynchronous packet to be transmitted. (the link will also be signaled that a packet is available for transmission if the entire packet is in the fifo, regardless of its size.) the threshold is 16 x n quadlets; n defaults to a value of 0x10 (256 quadlets). max size of n is 0x20 (512 quadlets). 15:12 at maximum burst the maximum number of quadlets that will be fetched by the at or physical read response dmas in one pci transaction. the maximum burst is 16 x (n + 1) quadlets; n defaults to 7 (128 quadlets). max value of n is 0xf. 11:8 at threshold this field defines the amount of available space that is needed in the at fifo, before the at or physical read response units will request access to the pci bus. the threshold is 16 x (n + 1) quadlets; n defaults to 0 (16 quadlets). note, however, that the at or physical dmas may request access to the pci bus sooner if the amount of data to be fetched from memory is less than the amount of space available in the at fifo. max value of n is 0xf. 7:4 ar maximum burst the maximum number of quadlets that will be written by the ar and physical write dmas in one pci transaction. the maximum burst is 16 x (n + 1) quadlets; n defaults to 7 (128 quadlets). max value of n is 0xf. 3:0 ar threshold this field defines the amount of available data that is needed in the ar fifo, before the ar dma will request access to the pci bus. the threshold is 16 x (n + 1) quadlets; n defaults to 0 (16 quadlets). however, the ar dma may request access to the pci bus sooner if the amount of data available in the fifo exceeds the space remaining in the current host memory buffer or a complete packet resides in the fifo. max value of n is 0xf.
agere systems inc. 67 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 5 internal registers (continued) 5.65 link options the values in this register provide low-level control of configurable features within the fw322 that are beyond those stated in 1394 and ohci specifications. offset: 840h default: 0000 0020h table 65. link options register description bits field description 31 ohci1.1en enables general features of ohci 1.1 that are not covered by any of the bits below. 30 reserved reserved for internal use by the fw322. must be set to 0x0. 29 regaccessfailen enables regaccessfailen interrupt for sclk register accesses that fail. 28 initbmenable enables usage of initial registers for loading bus management registers on a bus reset. 27 retryenable enables retry processing as defined in ohci 1.1. 26 configromenable enables config rom management, including config rom block reads, as defined in ohci 1.1. 25 dualbufferenable enables ir dual-buffer mode processing as defined in ohci 1.1 24 itchangeenable enables skip and fifo underrun processing in the it context as defined in ohci 1.1. 23 reserved reserved for internal use by the fw322. must be set to 0x0. 22 reserved read-only status bit. reserved for internal use by the fw322. will read back as 0x0. 21 reserved reserved for internal use by the fw322. must be set to 0x0. 20 reserved reserved for internal use by the fw322. must be set to 0x0. 19:6 reserved reserved for internal use by the fw322. must be set to 0x0. 5:3 posted writes number of physical posted writes the link is allowed to queue in the asynchronous receive fifo. these three bits [5:3] default to 100b, which is the maximum value. values greater than 100b will disable all physical posted writes. 2:0 cycle timer control selects the value the fw322 will use for its isochronous cycle period when the fw322 is the root node. this value is for debugging purposes only and should not be set to any value other than its default value in a real 1394 network. this value defaults to 0. if 0, cycle = 125 s. if 1, cycle = 62.5 s. if 2, cycle = 31.25 s. if 3, cycle = 15.625 s. if 4, cycle = 7.8125 s.
68 68 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 6 internal register configuration 6.1 phy core register map the phy core register map is shown below in figure 7. reference: ieee standard 1394a-2000, annex j2 figure 7. phy core register map address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0000 2 physical_id r ps 0001 2 rhb ibr gap_count 0010 2 extended (7) xxxxx total_ports 0011 2 max_speed xxxxx delay 0100 2 lctrl contender jitter pwr_class 0101 2 watchdog isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 0111 2 page_select xxxxx port_select 1000 2 register 0 page_select 1111 2 register 7 page_select required xxxxx reserved
agere systems inc. 69 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 6 internal register configuration (continued) 6.2 phy core register fields table 66. phy core register fields field size (in bits) type power reset value description physical_id 6 r 000000 the address of this node is determined during self-identification. a value of 63 indicates a misconfigur ed bus; therefore, the link will not transmit any packets. r 1 r 0 when set to one, indicates that this node is the root. ps 1r ? cable power active. the phy core sets this bit when cable power measured at the connector is at least 7.5 v. the phy core clears this bit when the detectable voltage is below this value. rhb 1rw 0 root hold-off bit. when set to one, the force_root variable is true. this instructs the phy core to attempt to become the root during the next tree identify process. ibr 1rw 0 initiate bus reset. when set to one, instructs the phy core to set ibr true and reset_time to reset_time. these values, in turn, cause the phy core to initiate a bus reset without arbitration; the reset signal is asserted for 166 s. this bit is self-clearing. gap_count 6rw 3f 16 used to configure the arbitration timer setting to optimize gap times according to the topology of the bus. see section 4.3.6 of ieee stan- dard 1394 a-2000 for the encoding of this field. extended 3 r 7 this field has a constant value of seven, which indicates the extended phy core register map. total_ports 4 r 3 the number of ports implemented by this phy core. this count reflects the number. max_speed 3r 010 2 this bit indicates the speed(s) this phy core supports: 000 2 = 98.304 mbits/s. 001 2 = 98.304 and 196.608 mbits/s. 010 2 = 98.304, 196.608, and 393.216 mbits/s. 011 2 = 98.304, 196.608, 393.216, and 786.43 mbits/s. 100 2 = 98.304, 196.608, 393.216, 786.432, and 1,572.864 mbits/s. 101 2 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and 3,145.728 mbits/s. all other values are reserved for future definition. pwr_class 3rw see description power class. controls the value of the pwr field transmitted in the selfid packet. see section 4.3.4.1 of ieee standard 1394 a-2000 for the encoding of this field. the pc0 pin determines the most signifi- cant bit of the power reset value. the two least significant bits, pc1 and pc2, are internally set to 0. the pc0 pin can be tied to v dd for power class 4, or tied to v ss for power class 0. watchdog 1 rw 0 when set to one, the phy core will set port_event to one if resume operations commence for any port. isbr 1 rw 0 initiate short (arbitrated) bus reset. a write of one to this bit instructs the phy core to set isbr true and reset_time to short_reset_time. these values, in turn, cause the phy core to arbitrate and issue a short bus reset. this bit is self-clearing. loop 1 rw 0 loop detect. a write of one to this bit clears it to zero. pwr_fail 1 rw 1 cable power failure detect. this bit is set to one when the ps bit changes from one to zero. a write of one to this bit clears it to zero.
70 70 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 6 internal register configuration (continued) table 66. phy core register fields (continued) field size (in bits) type power reset value description timeout 1 rw 0 arbitration state machine time-out. a write of one to this bit clears it to zero (see max_arb_state_time). port_event 1 rw 0 port event detect. the phy core sets this bit to one if any of con- nected, bias, disabled, or fault change for a port whose int_enable bit is one. the phy core also sets this bit to one if resume opera- tions commence for any port and watchdog bit is one. a write of one to this bit clears it to zero. enab_accel 1 rw 0 enable arbitration acceleration. when set to one, the phy core will use the enhancements specified in clause 4.4 of 1394 a-2000 specification . phy core behavior is unspecified if the value of enab_accel is changed while a bus request is pending. enab_multi 1 rw 0 enable multispeed packet concatenation. when set to one, the link will signal the speed of all packets to the phy core. page_select 3 rw 000 selects which of eight possible phy core register pages are acces- sible through the window at phy core register addresses 1000 2 through 1111 2 , inclusive. port_select 4 rw 0000 if the page selected by page_select presents per-port information, this field selects which port?s registers are accessible through the window at phy core register addresses 1000 2 through 1111 2 , inclu- sive. ports are numbered monotonically starting at zero, p0. delay 4 r 0000 worst-case repeater delay; total worst-case repeater delay = [144 + (delay x 20)] ns. lctrl 1rw 1 link active. cleared or set by software to control the value of the l bit transmitted in the node?s selfid packet 0, which will be the logi- cal and of this bit and lps active. contender 1rw see description cleared or set by software to control the value of the c bit transmit- ted in the selfid packet. powerup reset value is 0. jitter 3r 000 the difference between the fastest and slowest repeater data delay = [(jitter + 1) x 20] ns.
agere systems inc. 71 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 6 internal register configuration (continued) the port status page is used to access configuration and status information for each of the phy core?s ports. the port is selected by writing zero to page_select and the desired port number to port_select in the phy core register at address 0111 2 . the format of the port status page is illustrated in figure 8; reserved fields are shown as xxxxx. the meanings of the register fields in the port status page are defined as type rsc. figure 8. phy core register page 0: port status page the meaning of the register fields in the port status page are defined by table 67. address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1000 2 astat bstat child connected bias disabled 1001 2 negotiated_speed int_enable fault xxxxx xxxxx xxxxx 1010 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1011 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1100 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1101 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1111 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx required xxxxx reserved table 67. phy core register port status page fields field size type power reset value description astat 2 r ? tpa line state for the port: 00 2 = invalid. 01 2 = 1. 10 2 = 0. 11 2 = z. bstat 2 r ? tpb line state for the port (same encoding as astat). child 1 r 0 if this bit is equal to one, the port is a child; otherwise, a parent. the meaning of this bit is undefined from the time a bus reset is detected until the phy core transitions to state t1: child hand- shake during the tree identify process (see section 4.4.2.2 of ieee standard 1394a-2000). connected 1 r 0 if equal to one, the port is connected. bias 1 r 0 if equal to one, incoming tpbias is detected. disabled 1 rw 0 if equal to one, the port is disabled. negotiated_speed 3 r 000 this indicates the maximum speed negotiated between this phy core port and its immediately connected port; the encoding is the same as for the phy core register max_speed field (see table 66). int_enable 1 rw 0 enable port event interrupts. when set to one, the phy core will set port_event to one if any of connected, bias, disabled, or fault (for this port) change state. fault 1 rw 0 this bit is set to one if an error is detected during a suspend or resume operation. a write of one to this bit clears it to zero.
72 72 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 6 internal register configuration (continued) the vendor identification page is used to identify the phy core?s vendor and compliance level. the page is selected by writing one to page_select in the phy core register at address 0111 2 . the format of the vendor identi- fication page is shown in figure 9; reserved fields are shown as xxxxx. figure 9. phy core register page 1: vendor identification page address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1000 2 compliance_level 1001 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1010 2 1011 2 vendor_id 1100 2 1101 2 1110 2 product_id 1111 2 required xxxxx reserved note: the meaning of the register fields within t he vendor identification page are defined by table 68. table 68. phy core register vendor identification page fields field size type description compliance_level 8 r standard to which the phy core implementation complies: 0 = not specified. 1 = ieee 1394a-2000. agere?s fw322 compliance level is 1. all other values reserved for future standardization. vendor_id 24 r the company id or organizationally unique identifier (oui) of the manufacturer of the phy core. agere?s vendor id is 00601d h . this number is obtained from the ieee registration authority committee (rac). the most significant byte of vendor_id appears at phy core register location 1010 2 and the least significant at 1100 2 . product_id 24 r the meaning of this number is determined by the company or organization that has been granted vendor_id. agere?s fw322 phy core product id is 03226x 16 .* the most significant byte of product_id appears at phy core regis- ter location 1101 2 and the least significant at 1111 2 . * x is a minor revision number of the fw322 t100 and may be any value from 0 hex to f hex. note: the vendor-dependent page provides access to information used in the manufacturing test of the fw322.
agere systems inc. 73 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 7 crystal selection considerations the fw322 is designed to use an external 24.576 mhz parallel resonant fundamental mode crystal connected between the xi and xo terminals to provide the reference for an internal oscillator circuit. the ieee 1394a-2000 standard requires that fw322 have less than 100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. to achieve this, it is recommended that an oscillator with a nominal 50 ppm or less fre- quency tolerance be used. the total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm. 7.1 load capacitance the frequency of oscillation is dependent upon the load ca pacitance specified for the crystal, in parallel resonant mode crystal circuits. total load capacitance (c l ) is a function of not only the discrete load capacitors, but also capacitances from the fw322 board traces and capacitances of the other fw322 connected components. the val- ues for load capacitors (c a and c b ) should be calculated using this formula: c a = c b = (c l ? c stray ) 2 where: c l = load capacitance specified by the crystal manufacturer. c stray = capacitance of the board and the fw322, typically 2 pf?3 pf. r l = load resistance; nominal value is 400 ?; the best value to be used can be determined by customer testing. figure 10. crystal circuitry 7.2 adjustment to crystal loading the resistor (r l ) in figure 10 is recommended for fine-tuning the crystal circuit. the nominal value for this resistor is approximately 400 ?. a more precise value for this resistor is dependent on the specific crystal used. please refer to the crystal manufacturer?s data sheet and application notes to determine an appropriate value for r l . a more precise value for this resistor can be obtained by placing different values of rl on a production board and using an oscillo- scope to view the resultant clock waveform at node a for each resistor value. the desired waveform should have the following characteristics: the waveform should be sinusoidal, with an amplitude as large as possible, but not greater than 3.3 v or less than 0 v. 7.3 crystal/board layout the layout of the crystal portion of the phy circuit is important for obtaining the correct frequency and minimizing noise introduced into the fw322 pll. the crystal and two load capacitors (c a + c b ) should be considered as a unit during layout. they should be placed as close as possible to one another, while minimizing the loop area created by the combination of the three components. minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. this layout unit (crystal and load capacitors) should then be placed as close as possible to the phy xi and xo terminals to minimize trace lengths. vias should not be used to route the xi and xo signals. c b c a xi xo r l a
74 74 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 8 nand tree testing the fw322 can be placed into a nand tree mode of operation to enable board-level production testing. the nand tree mode is designed to allow board-level contact testing of the digital pins of the fw322. to place the fw322 into nand tree mode, pins 10 (test0), 7 (test1), and 124 (ptest) should all be forced high. (in normal mode, these inputs are forced low.) the output for nand tree is pin 6. no clocks are required for nand tree test- ing. when nand tree is enabled, the nand tree logic follows the signal ordering in table 69. to run the test, force all of the inputs in the table below high. at this point, the nand tree output should be verified to be high. in the order listed below, force each input low, while keeping previously tested inputs low. after each input is forced low, the nand tree output should be verified, and the correct value should be the opposite of the previous value. therefore, after forcing the first input low, the nand tree output should be low, after forcing the second input low (and keeping the first input low), nand tree output should be high, etc. table 69. nand tree testing input order pin # pin name input order pin # pin name 1 b1 cardbusn 35 m7 pci_stopn 2 c2 cna 36 n8 pci_devseln 3 a3 vaux_present 37 n7 pci_trdyn 4 b3 se 38 m6 pci_irdyn 5 a4 sm 39 n6 pci_framen 6 d5 resetn 40 m5 pci_cben[2] 7 e13 mpciactn 41 m4 pci_ad[16] 8e12lps 42 n5 pci_ad[17] 9 f10 lkon 43 n4 pci_ad[18] 10 f13 pc0 44 m3 pci_ad[19] 11 f12 pc1 45 m2 pci_ad[20] 12 g10 pc2 46 n3 pci_ad[21] 13 g12 contender 47 l3 pci_ad[22] 14 h10 pci_ad[0] 48 m1 pci_ad[23] 15 h13 pci_ad[1] 49 l2 pci_idsel 16 j10 pci_ad[2] 50 l1 pci_cben[3] 17 j12 pci_ad[3] 51 k2 pci_ad[24] 18 j13 pci_ad[4] 52 k4 pci_ad[25] 19 j9 pci_ad[5] 53 k1 pci_ad[26] 20 k13 pci_ad[6] 54 j2 pci_ad[27] 21 k10 pci_ad[7] 55 j1 pci_ad[28] 22 k12 pci_cben[0] 56 j4 pci_ad[29] 23 l12 pci_ad[8] 57 h2 pci_ad[30] 24 m13 pci_ad[9] 58 h1 pci_ad[31] 25 l11 pci_ad[10] 59 h4 pci_clk 26 m12 pci_ad[11] 60 g1 pci_reqn 27 m11 pci_ad[12] 61 f2 pci_gntn 28 n12 pci_ad[13] 62 f1 pci_rstn 29 m10 pci_ad[14] 63 e1 pci_intan 30 n11 pci_ad[15] 64 f4 clkrunn 31 m9 pci_cben[1] 65 d1 rom_ad 32 n10 pci_par 66 d2 rom_clk 33 n9 pci_serrn output c1 nandtree 34 m8 pci_perrn
agere systems inc. 75 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 8 nand tree testing (continued) figure 11. nand tree logic structure 9 solder reflow and handling the fw322 has a moisture sensitivity classification of 3, which is determined in accordance with the standard ipc/ jedec j-std-020, revision a, titled moisture/reflow sensitivity classification for nonhermetic solid state sur- face mount devices . handling of this device should be in accordance with standard ipc/jedec j-std-033, titled standard for handling, packing, shipping and use of moisture/reflow sensitive surface-mount devices . up to three reflows may be performed using a temperature profile that meets the requirements of table 3 in stan- dard ipc/jedec j-std-020. the requirements of ipc/jedec j-std-033 must be met. the maximum allowable body temperature for the fw322 is 220 c?225 c. this is the actual tolerance that agere uses to test the devices during preconditioning. 10 absolute maximum voltage/temperature ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 70. absolute maximum ratings parameter symbol min max unit supply voltage range v dd 3.0 3.6 v input voltage range v i ? 0.5 v dd + 0.5 v output voltage range at any output v o ? 0.5 v dd + 0.5 v operating free air temperature t a 070 c storage temperature range t stg ?65 150 c cna vaux_present se rom_ad rom_clk nandtree cardbusn vdd
76 76 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 11 electrical characteristics table 71. analog characteristics parameter test conditions symbol min typ max unit supply voltage source power node v dd?sp 3.0 3.3 3.6 v differential input voltage cable inputs, 100 mbits/s operation v id?100 142 ? 260 mv cable inputs, 200 mbits/s operation v id?200 132 ? 260 mv cable inputs, 400 mbits/s operation v id?400 100 ? 260 mv cable inputs, during arbitration v id?arb 168 ? 265 mv common-mode voltage source power mode tpb cable inputs, speed signaling off v cm 1.165 ? 2.515 v tpb cable inputs, s100 speed signaling on v cm?sp?100 1.165 ? 2.515 v tpb cable inputs, s200 speed signaling on v cm?sp?200 0.935 ? 2.515 v tpb cable inputs, s400 speed signaling on v cm?sp?400 0.532 ? 2.515 v common-mode voltage nonsource power mode* * for a node that does not source power (see section 4.2.2.2 in ieee 1394-1995 standard). tpb cable inputs, speed signaling off v cm 1.165 ? 2.015 v tpb cable inputs, s100 speed signaling on v cm?nsp?100 1.165 ? 2.015 v tpb cable inputs, s200 speed signaling on v cm?nsp?200 0.935 ? 2.015 v tpb cable inputs, s400 speed signaling on v cm?nsp?400 0.532 ? 2.015 v receive input jitter tpa, tpb cable inputs, 100 mbits/s operation ???1.08ns tpa, tpb cable inputs, 200 mbits/s operation ???0.5ns tpa, tpb cable inputs, 400 mbits/s operation ???0.315ns receive input skew between tpa and tpb cable inputs, 100 mbits/s operation ???0.8ns between tpa and tpb cable inputs, 200 mbits/s operation ???0.55ns between tpa and tpb cable inputs, 400 mbits/s operation ???0.5ns positive arbitration comparator input threshold voltage ?v th + 89 ? 168 mv negative arbitration comparator input threshold voltage ?v th ? ?168 ? ?89 mv speed signal input threshold voltage 200 mbits/s v th?s200 45 ? 139 mv 400 mbits/s v th?s400 266 ? 445 mv output current tpbias outputs i o ?5 ? 2.5 ma tpbias output voltage at rated i/o current v o 1.665 ? 2.015 v current source for connect detect circuit ?i cd ??76 a
agere systems inc. 77 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 11 electrical characteristics (continued) * this i dd value may differ depending on the system board into which the fw322 06 t100 pci add-in card is inserted. table 72. driver characteristics parameter test conditions symbol min typ max unit differential output voltage 56 ? load v od 172 ? 265 mv off-state common-mode voltage drivers disabled v off ??20mv driver differential current, tpa+, tpa ? , tpb+, tpb ? driver enabled, speed signaling off* * limits are defined as the algebraic sum of tpa+ and tpa ? driver currents. limits also apply to tpb+ and tpb ? as the algebraic sum of driver currents. i diff ? 1.05 ? 1.05 ma common-mode speed signaling current, tpb+, tpb ? 200 mbits/s speed signaling enabled i sp ? 2.53 ? ? 4.84 ma 400 mbits/s speed signaling enabled i sp ? 8.1 ? ? 12.4 ma table 73. device characteristics parameter test conditions symbol min typ max unit supply current: d0, 2 ports active d0, 1 port active d0, no ports active v dd = 3.3 v v dd = 3.3 v v dd = 3.3 v i dd i dd i dd ? ? ? 112 97 78 ? ? ? ma ma ma system in standby (suspend mode = s1) v dd = 3.3 v pci or v dd = 3.3 v aux i dd ?30?ma system in hibernate (suspend mode = s1 or s3) or system in standby (suspend mode = s3) v dd = 3.3 v aux i dd ?1.3?ma high-level output voltage i oh max, v dd = min v oh v dd ? 0.4 ? ? v low-level output voltage i ol min, v dd = max v ol ??0.4v high-level input voltage cmos inputs v ih 0.7 v dd ?? v low-level input voltage cmos inputs v il ??0.2v dd v pull-up current, resetn input v i = 0 v i i 11 ? 32 a
78 78 agere systems inc. fw322 nv129 1394a data sheet pci phy/link open host cont roller interface november 2005 12 timing characteristics table 74. switching characteristics symbol parameter measured test conditions min typ max unit ? jitter, transmit tpa, tpb ? ? ? 0.15 ns ? transmit skew between tpa and tpb ??? 0.1 ns t r rise time, transmit (tpa/tpb) 10% to 90% r i = 56 ?, c i = 10 pf ??1.2ns t f fall time, transmit (tpa/tpb) 90% to 10% r i = 56 ?, c i = 10 pf ??1.2ns table 75. clock characteristics symbol parameter min typ max unit f external clock source frequency 24.5735 24.5760 24.5785 mhz
agere systems inc. 79 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 13 outline diagram 13.1 129-ball vtfsbgac dimensions are in millimeters. ? ? 5() ? '(7$,/$ /2:(67%$//5()(5(1&(3/$1( 3$5$//(/72*/2%$/3/$1( */2%$/3/$1(,6%(67),7 3/$1($6'(7(50,1('%< &23/$1$5,7<0($685(0(17(48,30(17 '(7$,/$ 648$5( 7239,(: %$//*5,'$55$< &225',1$7(6)25 5()(5(1&(21/< $,1',&$725 7<362/'(5%$//6 %277209,(: %$//97)6%*$&
agere systems inc. reserves the right to make changes to the pr oduct(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are registered trademarks of agere systems inc. copyright ? 2005 agere systems inc. all rights reserved november 2005 ds06-018cmpr-1 (replaces ds06-018cmpr) for additional information, contact your agere systems account manager or the following: internet: home: http://www.agere.com sales: http://www.agere.com/sales e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: china: (86) 21-54614688 (shanghai), (86) 755-25881122 (shenzhen), (86) 10-65391096 (beijing) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6741-9855 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 1344 296 400 data sheet fw322 nv129 1394a november 2005 pci phy/link open host controller interface 14 ordering information * lead-free: no intentional addition of lead, and less than 1000 ppm. ? agere systems lead-free devices are fully comp liant with the restriction of hazardous substances (rohs) directive that restric ts the content of six hazardous substances in electronic equipment in the eu ropean union. beginning july 1, 2006, electronic equipment sold in the euro- pean union must be manufactured in accordance with the standards set by the rohs directive. microsoft and windows are registered trademarks of microsoft corporation. the firewire logo is a trademark and macos is a registered trademark of apple computer, inc. ieee is a registered trademark of the institute of electrical and electronics engineers, inc. mini pci is a registered trademark of pci-sig, inc. device code package comcode L-FW322-06-NV129-DB* ? 129-ball vtfsbgac 711006786 l-fw322-06-nv129-dt* ? 129-ball vtfsbgac 711006787

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